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mixed signal simulation

KUMARJAYA
is it possible to simulate verilog netlist in cadence virtuoso?how to bind the standard netlist cell to the corresponding code?
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  • thanks for your valuable guidance....

    sir,

    in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks.

    so i generate verilog netlist of the corresponding digital block.

    But after integrating it with analog block i need to check functional and transistor level behavior of corresponding standard cells in verilog netlist.

    is verilog or VHDL AMS as standard cell for verilog netlist ?

    if not please give some solution for it........  

     

      

Reply

  • thanks for your valuable guidance....

    sir,

    in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks.

    so i generate verilog netlist of the corresponding digital block.

    But after integrating it with analog block i need to check functional and transistor level behavior of corresponding standard cells in verilog netlist.

    is verilog or VHDL AMS as standard cell for verilog netlist ?

    if not please give some solution for it........  

     

      

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