thanks for your valuable guidance....
in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks.
so i generate verilog netlist of the corresponding digital block.
But after integrating it with analog block i need to check functional and transistor level behavior of corresponding standard cells in verilog netlist.
is verilog or VHDL AMS as standard cell for verilog netlist ?
if not please give some solution for it........