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mixed signal simulation

KUMARJAYA
is it possible to simulate verilog netlist in cadence virtuoso?how to bind the standard netlist cell to the corresponding code?
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  • That's exactly what AMS is for - you can have Verilog or VHDL or System Verilog or VerilogAMS or VHDL AMS descriptions of your blocks and simulate them in conjunction with pure analog parts (transistor level, or VerilogA). Standard cells would normally have either a Verilog or VHDL description (Verilog more commonly). 

    This is the kind of thing that the tutorial will show you how to use the hierarchy editor to pick appropriate views of each cell, and then simulate everything together.

    Unfortunately your question is extremely open ended (and not very clear) so it's hard to give a precise answer to a vague question...

    Regards,

    Andrew.

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  • That's exactly what AMS is for - you can have Verilog or VHDL or System Verilog or VerilogAMS or VHDL AMS descriptions of your blocks and simulate them in conjunction with pure analog parts (transistor level, or VerilogA). Standard cells would normally have either a Verilog or VHDL description (Verilog more commonly). 

    This is the kind of thing that the tutorial will show you how to use the hierarchy editor to pick appropriate views of each cell, and then simulate everything together.

    Unfortunately your question is extremely open ended (and not very clear) so it's hard to give a precise answer to a vague question...

    Regards,

    Andrew.

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