Verilog-a model instantiation

Hello Experts,

I am new to use of Verilog a models .
I have the code for mems switch using the verilog-a. Now I would like to instantiate the mems switch to work as a inverter. But I am getting error as below

ERROR (VACOMP-2259): "input vdd<<--? = 5;"

Code for  inverter model instantiation is as below. (i have written this code after the endmodule statement of MEMS switch)

module inverter(in, out, vdd, gnd);

input in;
output out;
electrical in, out;

electrical vdd,gnd;

input vdd = 5;
input gnd = 0;
mems mems_1(vdd, out, in); //actual model mems(s, d, g);
mems mems_2(out, gnd, in);
endmodule



Please help me.
Thank You