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Problem Simulating Verilog-AMS top cellview

GabrielB

Dear all,

 I created a Verilog-AMS cellview for describing the top-level of a test-chip, which contains  I/O pads, an analog block and some digital blocks. I decided to use VAMS because of the multiple supply voltages inside the chip and this helped me a lot semplifying the insertion and definition of connect rules.

However I get some problems when I switch the view of my analog block from schematic to analog_extracted (generated with assura QRC 10.1) since a bus port is expanded. I didn't find any way to force QRC preserving the bus so I tryed with the AMS option

  hnlVerilogTermSyncUp = "honorSM"

Netlisting is then possible, but simulation not: 

 *E,CUVPOM (/home/seproject/ares/work/bertotti/WORKBENCHES_MSF/chip_MuADC/verilogams/verilog.vams,80|10): Port name 'Dout' is invalid or has multiple connections.

Where the error referes to the instantiation in my VAMS file of the analog module and Dout is the port of the flattened bus.

myBlock analog_block ( ...... , .Dout (DATA_OUT), .... );

I guess the problem comes from the fact that the OSS netlister simply include the verilogams view of my chip without concatenating the single pins of the analog extracted view.

Any Idea to solve this problem?

With a schematic view I wouldn't have any problem, but i should start with a Verilog file and forget about any discipline spec...

Thanks in advance,

 Gabriel

 

 

Parents

  •  Sorry mates,

     I found it. Now my .simrc looks like this 

    simVerilogNetlistExplicit            = 't        ;ADE override this command - check it!!
    hnlVerilogTermSyncUp             = "honorSM"    ;For unpreserved buses in the switched view
    simVerilogFlattenBuses               = 'nil        ;Value for compatibility with TermSyncUp
    hnlVerilogNetlistNonStopCellExplicit = 't        ;Value for compatibility with TermSyncUp
    simVerilogDropPortRange             = 't        ;Value for compatibility with TermSyncUp

    and the netlisting of the analog block seems right.

    However I get some problems with the functional views of my std cells....  

    ERROR (OSSHNL-371): Netlisting failed because the terminal 'a' was not found on the instance

    'i6' in cellview 'IO_CELLS_F3V/BT2SF/functional'. Provide correct terminals on the instance by

    referring to its switched master and netlist again.

     

    i6 is a verilog primitive and in OA has all the terminals needed by its switch master.

     

    I'm using Virtuoso 6.1.6-64b.500.1 with Incisive 13.10.004

     

Reply

  •  Sorry mates,

     I found it. Now my .simrc looks like this 

    simVerilogNetlistExplicit            = 't        ;ADE override this command - check it!!
    hnlVerilogTermSyncUp             = "honorSM"    ;For unpreserved buses in the switched view
    simVerilogFlattenBuses               = 'nil        ;Value for compatibility with TermSyncUp
    hnlVerilogNetlistNonStopCellExplicit = 't        ;Value for compatibility with TermSyncUp
    simVerilogDropPortRange             = 't        ;Value for compatibility with TermSyncUp

    and the netlisting of the analog block seems right.

    However I get some problems with the functional views of my std cells....  

    ERROR (OSSHNL-371): Netlisting failed because the terminal 'a' was not found on the instance

    'i6' in cellview 'IO_CELLS_F3V/BT2SF/functional'. Provide correct terminals on the instance by

    referring to its switched master and netlist again.

     

    i6 is a verilog primitive and in OA has all the terminals needed by its switch master.

     

    I'm using Virtuoso 6.1.6-64b.500.1 with Incisive 13.10.004

     

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