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How to get the simulation results of internal node in verilog?

xxgenerall

Hi,

There is a very simple verilog code below.

And the internal node "tmp1" is present. Through Verilog-In, a symbol and a functional view can be obtained, like this.

 

Notice that there are only input and output ports in the symbol. After simulation in ADE, we can see results of these ports. However, internal node "tmp1" can't be seen, with no simulation results.

Is there any way of getting results of internal nodes in verilog?

Thanks in advance. 

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