Stats

  • Locked Locked
  • Replies 0
  • Subscribers 64
  • Views 12689
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Verilog-A Multiple variables of fixed size

Nick Martin

What would the proper syntax be to declare 256 integer variables with a width of 8?

integer A0[0:7], A1[0:7], ... , A255[0:7]; // without writing out all 256

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.