Stats

  • Locked Locked
  • Replies 8
  • Subscribers 65
  • Views 40175
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Verilog-A code for ADC

Julinshah

Hello,

I have Verilog-A code for Ideal ADC. I am using it in Virtuoso spectre and I am  not familiar with Verilog-A at all.
But this ADC works on the rising edge of the clock and I want my ADC to work on falling edge.

Can anyone please help which part of the verilog-A code I need to change so that I can make this work for falling edge.

Verilog-A code for ADC:

// FUNCTION: Analog to Digital Converter
// VERSION: $Revision: 2.12 $
// AUTHOR: Cadence Design Systems, Inc.
//
// GENERATED BY: Cadence Modelwriter 2.31
// ON: Fri Mar 07 09:37:38 EST 2008
//
// Description: Ideal Analog to Digital Converter
// Generates an N bit ADC.
// - selectable logic output levels
// - model valid for negative values of vmin
// - adjustable conversion time, and rise/fall time
// This model is an example, provided "as is" without express or
// implied warranty and with no claim as to its suitability for
// any purpose.
//
// PARAMETERS:
// slack = The smallest time interval considered negligible for
// cross event on clock [S]
// tconv = Delay from threshold crossing to output change [S]
// trise = Rise time for digital output signals [S]
// trise = Rise time for digital output signals [S]
// vmax = ADC Full scale output voltage [V]
// vmin = ADC Zero scale output voltage [V]
// vone = The voltage of a logical 1 on digital outputs [V]
// vth = Threshold value of clock signal [V]
// vzero = The voltage of a logical 0 on digital outputs [V]
//
`include "discipline.h"
`include "constants.h"
`define NUM_ADC_BITS 10
module adc_8bit (vin, clk, data);
input vin, clk;
electrical vin, clk;
output [`NUM_ADC_BITS-1:0] data;
electrical [`NUM_ADC_BITS-1:0] data;
parameter real vmax = 0.750;
parameter real vmin = 0.250;
parameter real one = 1.8;
parameter real zero =0;
parameter real vth = 0;
parameter real slack = 0.5p from (0:inf);
parameter real trise = 1.0p from (0:inf);
parameter real tfall = 1.0p from (0:inf);
parameter real tconv = 0.5p from [0:inf);
parameter integer traceflag = 1;
real sample, vref, lsb, voffset;
real vd[0:`NUM_ADC_BITS-1];
integer ii, binvalue;
analog begin
@(initial_step or initial_step("dc", "ac", "tran", "xf")) begin
vref = (vmax - vmin) / 2.0;
lsb = (vmax - vmin) / (1 << `NUM_ADC_BITS) ;
voffset = vmin;
if (traceflag)
$display("%M ADC range ( %g v ) / %d bits = lsb %g volts.\n",
vmax - vmin, `NUM_ADC_BITS, lsb );
generate i ( `NUM_ADC_BITS-1, 0) begin
vd[i] = 0 ;
end
end
@(cross ( V(clk)-vth, 1, slack, clk.potential.abstol)) begin
binvalue = 0;
sample = V(vin) - voffset;
for ( ii = `NUM_ADC_BITS -1 ; ii>=0 ; ii = ii -1 ) begin
vd[ii] = 0;
if (sample > vref ) begin
vd[ii] = one;
sample = sample - vref;
binvalue = binvalue + ( 1 << ii );
end
else begin
vd[ii] = zero;
end
sample = sample * 2.0;
end
if (traceflag)
$strobe("%M at %g sec. digital out: %d vin: %g (d2a: %g)\n",
$abstime, binvalue, V(vin), (binvalue*lsb)+voffset);
end
generate i ( `NUM_ADC_BITS-1, 0) begin
V(data[i]) <+ transition ( vd[i] , tconv, trise, tfall );
end
end
endmodule
`undef NUM_ADC_BITS

Thank you.

  • Hi Julin

    Please change the line from"@(cross ( V(clk)-vth, 1, slack, clk.potential.abstol)) begin"

    to "@(cross ( V(clk)-vth, -1, slack, clk.potential.abstol)) begin".

    The cross with "-1" will work for falling edge, as you requested.

    Have good simulation. Best regards, Andre.

  • Andre

    Thank you so much.

    That did help.

    Best regards,

    Julin.

  • Hii,

    I am also not familiar with VerilogA. So can anyone tell me which type of ADC the above code implements? Is it pipelined ADC?

  • in reply to ghota3

    It's actually an algorithmic ADC (as you can see, it find the residue after each bit, doubles it and then converts that to find the next bit). However, it's not really modelling a algorithmic or pipelined converter because there's no delay in conversion - the output appears in the same cycle that the input was sampled at. The internal loop is effectively implemented as an instantaneous algorithmic converter though.

    Andrew.

  • in reply to Andrew Beckett

    Thank You so much, Andrew. I had just one curiosity. Is this VerilogA model is synthesizable into its transistor level equivalent and if so, how can I evaluate the transistor level performance of this kind of ADC?

    Regards,

    G Hota.

  • in reply to ghota3

    No. Verilog-A is not synthesizable in any tool that I know of and even if it was in some selected situations, this is a behavioural model of an ideal converter. It would be extraordinarily hard for anything to figure out what would be a reasonable implementation (especially as it converts instantaneously; instantaneously is somewhat tricky in real life).

  • in reply to Andre Baguenie

    can anyone tell me what clk.potential.abstol means?is it define in discipline.h?

  • in reply to 433th

    Yes, it's define in discipline.h (aka disciplines.vams nowadays). The clk signal is define as discipline electrical and you'll see in the disciplines file (in the SPECTRE installation at <SPECTREinstDir>/tools.lnx86/spectre/etc/ahdl/disciplines.vams ) that electrical is defined as:

    discipline electrical
	potential    Voltage;
	flow         Current;
enddiscipline

    The potential and voltage are natures, which are defined in the file too.

    // Potential in volts
nature Voltage
	units      = "V";
	access     = V;
`ifdef VAMS_ELEC_DIS_ONLY
`else
	idt_nature = Flux;
`endif
`ifdef VOLTAGE_ABSTOL
	abstol     = `VOLTAGE_ABSTOL;
`else
	abstol     = 1e-6;
`endif
endnature

    From this you can see that the definition of a nature includes information about the units (for display purposes), the access function (so this is what defines that V(a,b) is how you access the voltage and some other key attributes, such as the absolute tolerance - can also set things like blowup limits and so on.The absolute and relative tolerance (relative tolerance is a simulator option) are used all over the place for convergence criteria so that the iterated methods know when to stop - and the absolute tolerance sets what is usually a small enough signal where the difference is such that the results are deemed to be accurate enough (usually a millionth of a typical signal level is about right for this). As you can see, it can be overridden too by using:

    `define VOLTAGE_ABSTOL 1e-5

    in your VerilogA before the `include "discipline.h"

    Regards,

    Andrew.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.