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CPF supported multi power domain Verilog to Netlist conversion

HansRey

Hi,


I'm using the cadence digital design flow including RTL Compiler and SoC Encounter. I made a multi power domain design using the CPF files and low power modes of the programs. For final signoff and lvs, I want to extract a spice netlist of the design. Is it possible to do this in a 'correct' way using the power domain definitions of the CPF file? I know programs like v2s or v2lvs, but these are all 'flat' verilog to spice converters...

Kind regards,

Hans

  • Hello Hans,

    In case of using PVS you could specify the optional CPF import to run LVS.

    Add an option to export a CDL after extraction (lvs_write_netlist).

     

    Another way is to make use of Virtuoso. Import the Verilog to generate a schematic and in Schematic XL you run import power intent to load the CPF file used in EDI and generate all required netSet automated.

    When done and verified you could use Tools – Export – CDL to generate a CDL netlist.

    If you’re interested in this flow – we do have a Rapid Adoption Kit (RAK) at support.cadence.com available.

     

    Kind Regards

    Andreas

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