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AMS Verilog module parameter passing

Cogito

Hi,

I'm running AMS / cds-incisiv / irun and I've run into an issue.  (cds-incisiv is version 14.20.009-64).  I have Verilog module statements like the following:

module mymod  #(`include "mymod_params.v") ( ...

The irun simulator does not like that syntax.  I get an ncvlog error:

`include directive not isolated on its own line [16.5(IEEE)].

The simulation works if I use the older notation:

module mymod #(param myparam=1) (...

Is there a switch I can set that will force the simulator to use the newer syntax?  Is there a way around this?  Is this slated to be fixed?  I have many modules that I do not to be forced to modify.

Thanks much,

Eric

Parents

  • Eric,

    I'm not sure why you say "force the simulator to use the newer syntax". The `include within the parameter list is not "newer syntax". According to the IEEE 1364-2005 Verilog LRM, in section 19.5 it says:

    Only white space or a comment may appear on the same line as the `include compiler directive.

    so what you've typed is not legal according to the LRM. The 16.5 is (I think) a reference to the same section in the 1995 LRM. The same line appears in section 22.4 of the SystemVerilog LRM (IEEE 1800-2009 and the same section number in IEEE 1800-2012).

    So why do you think this is legal?

    Regards,

    Andrew.

Reply

  • Eric,

    I'm not sure why you say "force the simulator to use the newer syntax". The `include within the parameter list is not "newer syntax". According to the IEEE 1364-2005 Verilog LRM, in section 19.5 it says:

    Only white space or a comment may appear on the same line as the `include compiler directive.

    so what you've typed is not legal according to the LRM. The 16.5 is (I think) a reference to the same section in the 1995 LRM. The same line appears in section 22.4 of the SystemVerilog LRM (IEEE 1800-2009 and the same section number in IEEE 1800-2012).

    So why do you think this is legal?

    Regards,

    Andrew.

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