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How to use AMS design flow with standard cell library?

dogrush

I want to try the AMS flow with standard cell library.

Digital part will be implemented using synthesis from the RTL level, under the standard cell library.

Analog part will be designed by ourselves as layout level, and for high level evaluation it can be described by VerilogA model.

I am wondering how to verify the whole design? How to do the simulation?

Analog-centric or digital-centric?

I have tried some demo, such as the AMSD flow from the "Workshop for AMSD Virtuoso Use Model". But it seems that there is no layout or standard cell involved.

So, is there someone familiar with this problem? Or suggestions?

Thanks.

Jerry

  • Additional notes:

    I use the standard cell library to implement the digital part. That is, no detailed information available for the gate instances, just the Synopsys lib available for timing information.

    If the RTL design is synthesized as gate level using DC, and implemented as physical level using encounter or astro.

    My question is, how to do the simulation?

    It seems that cadence provides some ams flow, but doesn't support the simulation with synopsys lib?

    Such as, using ultrasim to perform simulation, I have not found how to specify the synopsys lib for the timing information.

    Anyone who knows about it?

    Thanks.

    -Jerry

  • You wouldn't use a ".lib" file (or a "Liberty" file directly anyway - you'd need to run a delay calculator (e.g. Cadence Tempus or Synopsys PrimeTime) to generate SDF and then annotate the SDF in the simulation.

    The digital part can then be handled using the Verilog models of the standard cells, with the SDF delays annotated on during the simulation. That's covered in the documentation.

    Regards,

    Andrew.

  • Fine. I will try the back annotation solution, hope it work.

    Thanks.

    Jerry

  • in reply to Andrew Beckett

    Hello Andrew,

    I want to know as to how can I annotate SDF timing information in AMS simulator.

    Regards,

    Bijoy

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