too few terminals given

Hi,

Spectre seems to find fault with a veriloga model I used and the error message shows as below: 

ERROR (CMI-2116) : too few terminals given (15<17) ....

I searched the forum, there are a few thread related, but doesn't seems quite applicable to this case, which is a pure analog testbech with just this one block in veriloga.

I also added the veriloga model as below, main function is to serilize.

Could someone please take a look?

Thanks!

Kev

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`include "constants.vams"
`include "disciplines.vams"

module testmod(in,vdd,clk,rstn,out,itest);

input [11:0] in;
electrical [11:0] in;

input vdd,clk,rstn;
electrical vdd,clk,rstn;

output out, itest;
electrical out, itest;

real vdd_v, vth, out_v, rstn_v,itest_v, in_v[11:0];

integer i,k,delay;

analog begin

    vdd_v = V(vdd);
    vth = vdd_v/2;
    delay = 0;
    rstn_v = V(rstn);
       
      @(cross(V(clk) - vth, 1))
      begin
           if (rstn_v < vth)
          begin
             i = 0;      
                 out_v = 0;
          end
       
       else if (i > 11)
             begin
            i = 0;
                generate k (0,11)  
            in_v[k]=V(in[k]);            
             end
         
          out_v = in_v[i];
          i=i+1;         
      end
      
      itest_v=i-1;
      V(out) <+ transition(out_v, 10p, 10p, 10p);
      V(itest) <+ transition(itest_v, 10p, 10p, 10p);
      
end
endmodule