How to instantiate module ports by name when port bus defined individually - VerilogAMS

We are trying to instantiate a schematic in a top level verilogams test bench. The netlist of the schematic that ADE generates using AMS-UNL netlister looks slightly weird as given below

module abc(a,b,{c[2],c[1]},d);

input [2:1] a;

input [1:2] b;

input [1:2] c;

output d;

I am not sure why port c alone is defined as {c[2],c[1]} instead of simply c. What could be the reason?

When I try to instantiate this module in a top level ams testbench I am not sure how to pass values to port c by name.

I tried

abc    I_abc (.a(x1), .b(x1), .c(x3), .d(y)); and

abc    I_abc (.a(x1), .b(x1), .{c[2],c[1]}(x3), .d(y));

Is there a way to make this work?

We copied the netlist and manually replaced {c[2],c[1]} with c and saved it as a verilogams and used it instead of schematic and it works.

Also I observed that the netlister issues several warnings of the kind "port uses both ascending and descending ranges.

The bus will be declared with a 'ascending' range as specified by the skill

flag 'hnlSetBusDirectionDescending'."

I used to get these warnings in previous designs as well but the netlist never had this issue.

In the .simrc file I added the line  hnlSetBusDirectionDescending = t

Now the netlist comes out correctly as c instead of {c[2],c[1]} and the instantiation works. But I am not sure if this flag will break something else.

So here are my questions summarized.

1. How to pass ports when the port in the module is defined as {c[2],c[1]} ?

2. Why does the port gets defined as {c[2],c[1]} when other ports are correct ?

3. What are the potential side effects of the flag hnlSetBusDirectionDescending = t ?