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AMS simulation - logic clock wrongly translated into analog then back to logic due to connect modules

MonEcran

Hi,

I am running an AMS simulation of a chip with both digital and analog.

I have a clock generated by my digital (the clock is a logic signal inside the digital block).

The clock is received within the analog by an inverter that I set as a systemverilog model so that the clock should remain logic.

However the clock is translated into electrical at the top level (where both digital and analog block are instanciated).

This slows down my simulation.

I have already checked that nothing else is connected to this net.

How can I make sure that no connect modules are inserted in the path (between the clock from the digital and my inverter in systemverilog with input defined as a logic)?

Thanks by advance for your help.

incisiv/14/14.20.007

mmsim/14/14.10.576

ic/IC617/IC_617_701

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