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  3. Convergence Issue

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Convergence Issue

Charanraj Mohan
Charanraj Mohan over 9 years ago

Hey I am using Cadence IC 6.1.6 & UMC 130nm technology

I have a big schematic and am running simulation in transient of 100us simulation time. I face some difficulties with convergence issues for which I tried the following-

1. With 'trap' the simulation becomes slower at 41%. Before 41% the step was in nano second and micro second.At 41% it became to Armstrong and femto seconds and became dead slow. In fact it did not cross 41 % simulation time. I lost my patience after i ran for several minutes. But I could see the expected output until 41% simulation time.

2. When I tried 'Euler', the same happened at 10.7% of simulation time i.e. in the beginning itself.

3. When I tried 'traponly' i get same results as in 1. But I get trapezoidal ringing at 4 nodes along with the expected output until 41% simulation time as observed in 1.

4. When I tried 'gear2', I get convergence problem at 7.28% of simulation time.

5. For 'gear2only' the convergence problem occurs at 6.5% of simulation time.

6. For 'trapgear2', it occurs at 8.49 % simulation time.

In 'trap' method there is no convergence issue until 40 us. After this only I get problems.

I have two questions-

a. How should I handle these non convergences ?

b. Is there any accelerator option in Cadence IC 6.1.6 simulation as in MATLAB ?

thanks in advance

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  • Charanraj Mohan
    Charanraj Mohan over 9 years ago

    Thanks Andrew.

    :-)

    I sorted it. I enabled 'allglobal' in refrel of accuracy parameter option in simulation. Then when I ran the simulation, there was no convergence problem. Earlier it was 'sigglobal' by default.

    It seems that each kit has its own default convergence settings & it simulates by it unless we change the options.

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  • Charanraj Mohan
    Charanraj Mohan over 9 years ago

    Thanks Andrew.

    :-)

    I sorted it. I enabled 'allglobal' in refrel of accuracy parameter option in simulation. Then when I ran the simulation, there was no convergence problem. Earlier it was 'sigglobal' by default.

    It seems that each kit has its own default convergence settings & it simulates by it unless we change the options.

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