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  3. Ignoring or avoiding "x" propagtaion for ams simulation...

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Ignoring or avoiding "x" propagtaion for ams simulation for certain signals and/or instances due to connect module definitions

MDiaz
MDiaz over 8 years ago

Hi,

  When running an ams simulation.  I know one can remove the "x" propagation due to timing checks with standard cells by using the -tcheck or -timing option.  I think I've learned that this only stops x propgation for setup and hold time violations which works fine any time I have signals that are truly asynchronouos Data or Resets going into a flip flop where if I have a setup and hold issue I ignore the timing viloation and allow what would cause an x propagation at the Q line (if CLock and data don't have enough setup and or hold time, or a reset to a flop comes at the same time the clock does) to what I'm guessing preserves its last state.  However I learned X propagation due to slow "slewing signals" are caused by connect module definitions and can not be ignored using the -tcheck or -timing options. Is there a way to no allow X propagation for certain instances that occur during these slow slewinging conditions and/or startup? 

Example being an RC going into a logic gate if the net is slewing slower than the connect module definitions it will propagate an X until the slewing net crosses some defined threshold, to avoid this I normally just make any logic gate that I know has a slow slewing net a schematic, but it would be much easier if I had some common instance name where I can use some wild card to remove this for all cells exhibiting this behavior i.e.

if I have multiple logic gates that have slow slewing inputs with an instance name with a prefix ISLOWSLEW_instanceN  I can create a file with some sort of wild card defintiion that has a statement as below:


TB.CELLTOP.*ISLOWSLEW*   -turn off X propagation  where this will not allow an X propagation for any instances that are within a testbench called TB in all levels of hierarchy inside CELLTOP that have "ISLOWSLEW" in its instance name.  

An analogy for timing checks for standard cells I would use the following:

TB.CELLTOP... -tcheck this would turn off all timing checks for cells within CELLTOP and any level of hierarhy. 

I don't want to change the connect module definitions because I would only like to change them for the cells I know whose states are only being "undefined" during that moment of time because the signals driving them may be filtered.

I am using virtuoso version 6.1.7 with AMS irun (not sure what version).

Thanks

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  • Andrew Beckett
    Andrew Beckett over 8 years ago

    I've never used the -tcheck or -timing options (not sure they're appropriate here), so can't really comment on the feasibility of using something similar (without spending time doing research to try it out).

    Wouldn't it be better to change the connect rule definitions for the specific instance ports in question (you don't need to change the global settings - just change the behaviour for the specific nets you want to prevent the slow rise/fall causing a problem). For example, if you use the Setup->Connect Rules/IE Setup form, particularly using the Interface Element setup form which has a much simplified user interface, you can specify the global settings you want to use, and then have different settings for a more specific scope.

    Regards,

    Andrew.

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  • MDiaz
    MDiaz over 8 years ago
    Hey Andrew, Thanks for the input. I think that leads me in the right direction. That being said we do have global custom connect rules that work for the most general cases. Is there a way I can make a seperate file that overwrites certain portions of the global connect rules for selected instances and just add that file to the list of connect Rules used in simulation under the Connect Rule/Connect Module Based Setup section? After playing with the Connect Rules/IE Setup form this does work but seems very "brute force", since we work on larger chips its tough to navigate and get all of them at the top. With this ability I could ask others to just append the instance names (to said file) that exhibit the behavior we're trying to modify the connect rules for.

    Thanks again,
    Mhanny
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  • Andrew Beckett
    Andrew Beckett over 8 years ago

    Hi Mhanny,

    Not really in ADE (at least not that easily). Could be worth talking to customer support to see if we can figure out a better flow.

    One way that comes to mind is to actually create a new (say) logic discipline (called, for example, logicNoX) and then define connect rules for that discipline. Then you can add the netDiscipline property to wires in the design and then don't have to set all this up each and every time in ADE. Again, the kind of thing that's worth talking through with customer support or your account team.

    Regards,

    Andrew.

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