No connection module found:Need an input port of continuous discipline electrical, and an output port of discrete discipline logic

Hi All,

I am new to this AMS simulations, I am facing issues during the elaboration

`include "disciplines.vams"
(* cds_ams_schematic *)
module FLASH_ADC_TB ( o,D,AVDD,AVSS,IBIAS,VSUP,PBKG,VREF );

output [2:0] o;
logic [2:0] o;
output [6:0] D;
logic [6:0] D;

electrical AVDD;
electrical AVSS;
electrical IBIAS;
electrical VSUP;
electrical PBKG;
electrical VREF;

electrical net2;
electrical net7;

FLASH_ADC (*
integer library_binding = "PUNEETH_BQFXX";
*)
I0 ( .VIN_N(
net2 ), .AVSS( AVSS ), .D1( D[1] ), .D3( D[3] ), .VIN_P( VSUP ), .D2(
D[2] ), .D4( D[4] ), .D5( D[5] ), .D6( D[6] ), .PBKG( PBKG ), .IBIAS(
IBIAS ), .AVDD( AVDD ), .DO( D[0] ) );

vsource #(.type("dc"), .dc(4)) (*
integer library_binding
= "analogLib";
*)

ncelab: *E,CUVNCM (./source/digital/verilog.vams,40|28): No connection module found:Need an input port of continuous discipline electrical, and an output port of discrete discipline logic, at instance FLASH_ADC_TB.I0.
net2 ), .AVSS( AVSS ), .D1( D[1] ), .D3( D[3] ), .VIN_P( VSUP ), .D2(
|
ncelab: *E,CUVNCM (./source/digital/verilog.vams,40|41): No connection module found:Need an input port of continuous discipline electrical, and an output port of discrete discipline logic, at instance FLASH_ADC_TB.I0.
D[2] ), .D4( D[4] ), .D5( D[5] ), .D6( D[6] ), .PBKG( PBKG ), .IBIAS(
|
ncelab: *E,CUVNCM (./source/digital/verilog.vams,41|0): No connection module found:Need an input port of continuous discipline electrical, and an output port of discrete discipline logic, at instance FLASH_ADC_TB.I0.
D[2] ), .D4( D[4] ), .D5( D[5] ), .D6( D[6] ), .PBKG( PBKG ), .IBIAS(
|
ncelab: *E,CUVNCM (./source/digital/verilog.vams,41|13): No connection module found:Need an input port of continuous discipline electrical, and an output port of discrete discipline logic, at instance FLASH_ADC_TB.I0.
D[2] ), .D4( D[4] ), .D5( D[5] ), .D6( D[6] ), .PBKG( PBKG ), .IBIAS(
|
ncelab: *E,CUVNCM (./source/digital/verilog.vams,41|26): No connection module found:Need an input port of continuous discipline electrical, and an output port of discrete discipline logic, at instance FLASH_ADC_TB.I0.
D[2] ), .D4( D[4] ), .D5( D[5] ), .D6( D[6] ), .PBKG( PBKG ), .IBIAS(

My ncelab command : ncelab worklib.FLASH_ADC_TB -snapshot FLASH_ADC_TB:snapshot -MESSAGES -timescale 1ns/100ps -iereport ConnRules_5V_basic cds_globals -discipline logic -DRESOLUTION

I have defined Connect rules properly, i even declared the output as logic and wires as electrical but still i am wrong somewhere please help me out.

Thanks in advance!!!!!