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verilogA simulation of 2nd order Sigma-Delta modulator

VivekNITg

Dear Andrew,

I am simulating a 2nd order sigma delta modulator (with negative feedback) using the modelwritter (verilogA) blocks like discrete time integrators and ADC (4-bit) and DAC (4-bit).

But the output of the integrator is non-converging and the out of the integrators is coming in Mega Volts range.

Input Conditions are 100 mV sinusoidal signal of frequency 22 kHz and sampling frequency of 2.8 MHz.

outputs of sample and hold circuit, ADC and DAC are perfect (all are verilogA model blocks only) when used without integrator block.

As soon as integrator (delayed / non-delayed integrator) block is added the output of the integrators becomes non-convergent in nature.

Please help in this matter. I am attaching the circuit diagram of the Sigma-Delta Modulator.

  • First of all, this is a community forum - it's not an "ask Andrew" forum. I do this in my spare time (it's not part of my job) - I squeeze responses in when I can.

    I'm not going to sit and re-enter the schematic and guess what you've chosen on the model writer settings to produce each model - I simply don't have the time. Maybe somebody else would be more generous, but I suggest  you contact customer support with a complete testcase. The chances are you've accidentally created a positive feedback loop, but without seeing the actual data it would be hard to determine that.

    Regards,

    Andrew.

  • Dear ,

    I know that you have posted the above question a while ago, but I was wondering if you could share your experience with me. because I have the same issue as what you mentioned above. I am simulating a continuous time 2nd order sigma delta using veriloga blocks in Spectre, and the output voltage of the integrators are in the range of Mega Volts. I would appreciate if you could explain what was the issue in your case. I can also attach the code for each block and the schematic if that helps. Thank you.

  • in reply to ICFM

    Hey,

    I didn't have the solution to this problem I tried but couldn't get the right answer for the same. Instead, I used Ideal VCVS and other models from the analogue library and realises the operational amplifier and other blocks of the sigma-delta modulator i.e. sampler, integrator and comparator. So, I would suggest you use VCVS and other models.

  • in reply to VivekNITg

    I would suggest working with customer support on this as I stated a couple of years ago in my previous response to the original question. That would allow more detailed investigation of what is wrong with your models (or system) that would cause such a problem.

    Regards,

    Andrew.

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