Stats

  • Locked Locked
  • Replies 1
  • Subscribers 64
  • Views 14412
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

verilogA inlude search path

AdapSamp

Dear All

I have a couple of questions about verilogA, one on search path for include files and the other on using veriloga model without creating a veriloga view.

First, related to the search path for the includes, how would I set a list of paths to search for the include files. On a related note, does referencing a path as

`include"~/somepath"

not valid?  It gives a syntax error when attempted to do so.

Secondly, suppose I have a module, say resistor in a veriloga file named resistor.va. How may I associate an existing symbol view of a cell with  this veriloga module instead of creating a veriloga view. For example, if I instantiate the symbol of the cell under question in a schematic and netlist it, it should include the veriloga file (resistor.va, in this case) associated with it.

Thanks and regards

  • You can't use ~ in pathnames which are tick-included in VerilogA. The ~ representation of a home directory is a csh-thing, not a standard UNIX feature.

    What you can however do is just do:

    `include "somepath"

    and then on the spectre command line add -I$HOME to include your home dir in the search path. Or if you're using ADE, you can use the Include Path on Setup->Simulation Files to reference your home dir.

    If you want to include a VerilogA module not as a view, you'd have to ensure that there is a stopping view for that block (e.g. copy the symbol view to spectre, or mark it as a stop point in the hierarchy editor) and then define the CDF for the block so that it knows the name of the module and the terminal order (this is in the spectre simulation information). There are countless forum posts (and a blog from Tawna) telling  you how to do this. To include the actual Verilog-A code in the simulation, you'd need to add a model file (myVerilogA.scs, say) in Setup->Model Libraries which has the entry:

    ahdl_include "/path/to/resistor.va"

    Regards,

    Andrew.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.