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Connecting SPICE ports inside a SystemVerilog-only testbench

Dear all,

I'm trying to setup a mixed-signal simulation using SystemVerilog RNM and a transistor-level Spectre netlist for an analog block. I know that Verilog-AMS wreal nets can directly drive SPICE ports. Indeed, I want to use SystemVerilog-only constructs in my testbench, without the usage of Verilog-AMS constructs. However a direct connection between a real number and a SPICE port in not allowed since real is a discrete quantity. Does SystemVerilog allow to do this?

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