Constraining inputs for digital block in analog-on-top design

Hi,

I'm having some issues finding the right way to constrain some inputs coming from the analog section of our design.  What needs to be done is to sample a signal that can  change right after the clock edge (about ~10 ps), up to ~400 ps before the next clock edge. The clock period is 3.2ns. I would like the tool to add some bufffering, but not too much so that both setup and hold are respected. I've read the documentation of set_input_delay but I still find it a bit confusing, specially the use of the -min and -max option. I have tried the following two approaches:

set_input_delay  2.8   [get_ports {align_flag}] -clock clk

and

set_input_delay  -max  2.8    [get_ports {align_flag}] -clock clk

set_input_delay  -min .01  [get_ports {align_flag}] -clock clk -add_delay

I seem to be able to close timing with both according to my generated reports approaches, but when doing an SDF back-annotated simulation I still get  setup/hold issues sometimes, which tells me that what I am trying to ask the tool to do is not in line with my constraints. Should I take into account other factors when constraining my input ? (e.g. the insertion delay of my clock is ~150ps).

Thanks

JC