Extracted View Netlisting Issue

Hi all,

i have got an issue with the netlisting of my mixed signal design (using the UNL Flow):

I am running a "text on top" design from ADE Assembler with a config view - toplevel being a verilog view and an instance being a schematic view.

This worked fine until i tried to exchange the schematic view with an av_extracted view (created with PVS/ QRC).

The netlist with the schematic looked like this:

Module:

module SCHEMATIC_MODULE_NAME (BUS_NAME_A);
output [3:0] BUS_NAME_A;

...

...

..
endmodule

Instantiation:

wire [3:0] bus_wire;

SCHEMATIC_MODULE_NAME INSTANCE_NAME ( .BUSNAME_A(bus_wire));

which worked fine.

Now, the extraction view is netlisted as:

module SCHEMATIC_MODULE_NAME  (\BUSNAME_A(3) , \BUSNAME_A(2) , \BUSNAME_A(1) , \BUSNAME_A(0));

output \BUSNAME_A(3), \BUSNAME_A(2), \BUSNAME_A(1), BUSNAME_A(0);

.

.

.

endmodule

Which gives an error during elaboration....

I found that i can add a callProc.il to the QRC run in order to get [ ] brackets instead of parathesis (), but still the bus is split in this way, which means the simulation does not work.

Is there a way to get the extracted_view netlisted "the right way"?

Best regards,

Markus