Conditional Expression in Design Variable in AMS

This is a really simple test case to  show the issue with the conditional expression in a design variable in AMS. The pure Spectre simulator works fine with the conditional expression in a design variable and I can simulate with Spectre without any problem. However, when I switch the simulator into AMS, the AMS Unified Netlister with irun complains:

1/(X==1?1:6)
             ^^
SYNTAX ERROR found at line 1 column 8 of file *string*
*Error* lineread/read: syntax error encountered in input
<<< Stack Trace >>>
(... in _amsaWriteDesignVariablesInfoToFile ...)
(... in _amsaGenCdsGlobals ...)
(... in _amsaCreateCdsGlobals (ams_session) ...)
_amsaCreateCdsGlobals(stdobj@0x3ebc83c8)
(... in asiApply ...)
(... in asiExecuteFlowchartStep ...)
(... in asiExecuteFlowchart ...)
(... in asiGenerateNetlist (asiAnalog_session) ...)
(... in asiRecreateNetlist (ams_session) ...)
funobj:asiRecreateNetlist(stdobj@0x3ebc83c8)
(... in _sevNetlistFile ...)
(... in sevNetlistFile ...)
sevNetlistFile(sevSession16 recreate)

Here is Virtuoso version:

"@(#)$CDS: virtuoso version ICADV12.3-64b 06/01/2017 15:59 (sjfhw311) $"

Here is the Spectre netlist so that I do not need to upload the schematic (the circuit does not matter in this test  case) and ADE settings:

// Generated for: spectre
// Generated on: Sep 28 10:30:13 2017
// Design library name: mylib
// Design cell name: conditiondesvar
// Design view name: config
simulator lang=spectre
global 0
parameters X=6 R=1/(X==1?1:6)
include "/models/toplevel.scs" section=tt

// Library name: mylib
// Cell name: conditiondesvar
// View name: schematic
// Inherited view list: spectre spice pspice verilog verilogams behavioral
// functional systemVerilog schematic veriloga vhdl vhdlams wreal
V0 (net2 0) vsource dc=1 type=dc
R0 (net2 0) resistor r=R
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
tran tran stop=10n write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save R0:1
saveOptions options save=allpub

If I insert spaces around the '?' in the conditional expression, the AMS netlist succeeds, however the simulation fails with:

irun(64): 15.10-s002: (c) Copyright 1995-2015 Cadence Design Systems, Inc.

Fatal error found by spectre during hierarchy flattening.

FATAL (SFE-1996):
"/simulation/conditiondesvar/ams/config/netlist/cds_globals.vams"
25: Parameter `R': Attempt to divide by zero (1 / 0).

Here is the AMS netlist:

////////////////////////////////////////////////////////////////////////
// PLEASE DO NOT EDIT OR COMPILE THIS FILE.
// IT IS MEANT FOR VIEWING PURPOSE ONLY.
//
// All files for configuration: (mylib conditiondesvar config)
////////////////////////////////////////////////////////////////////////

// AMS netlist generated by the AMS Unified netlister
// IC subversion: ICADV12.3-64b.500.12
// IUS version: 15.10-s002
// Copyright(C) 2005-2009, Cadence Design Systems, Inc
// User: twen Pid: 7577
// Design library name: mylib
// Design cell name: conditiondesvar
// Design view name: config
// Solver: Spectre

`include "disciplines.vams"
`include "userDisciplines.vams"
// Library - mylib, Cell - conditiondesvar, View - schematic
// LAST TIME SAVED: Sep 28 10:18:29 2017
// NETLIST TIME: Sep 28 10:44:54 2017

`worklib mylib
`view schematic

`timescale 1ns / 1ns
(* cds_ams_schematic *)

module conditiondesvar ( );
vsource #(.dc(1), .type("dc")) V0 (net2, cds_globals.\gnd! );
resistor #(.r(cds_globals.R)) R0 (net2, cds_globals.\gnd! );

endmodule
`noworklib
`noview
// Verilog-AMS cds_globals module for top-level cell:
// mylib/conditiondesvar.
// Generated by ADE.
// Cadence Design Systems, Inc.

// This is an autoGenerated file, any changes done to this file may get lost.

`include "disciplines.vams"
`include "userDisciplines.vams"

module cds_globals;

// Global Signals
electrical \gnd! ;
ground \gnd! ;

// Design Variables
dynamicparam real X = 6;
dynamicparam real R = 1/(X==1 ? 1:6);

endmodule

// This is the Cadence AMS Designer(R) analog simulation control file.
// It specifies the options and analyses for the Spectre analog solver.

simulator lang=spectre

global 0

simulatorOptions options temp=27 tnom=27 scale=1.0 scalem=1.0 reltol=1e-3 \
vabstol=1e-6 iabstol=1e-12 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 pivrel=1e-3 checklimitdest=psf

tran tran stop=10n write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5

finalTimeOP info what=oppoint where=rawfile

modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile

wave_out options rawfmt=sst2

// This is the Cadence AMS Designer(R) analog simulation control file.
// Generated 'ie' card statement for the Connect Rules.
// TIME : Sep 28 10:44:56 2017
// IC subversion: ICADV12.3-64b.500.12
// IUS version: 15.10-s002

amsd{
ie vsup=1.8 discipline=logic
}

# This is the NC-SIM(R) probe command file
# used in the AMS-ADE integration.

#
# Database settings
#
if { [info exists ::env(AMS_RESULTS_DIR) ] } { set AMS_RESULTS_DIR $env(AMS_RESULTS_DIR)} else {set AMS_RESULTS_DIR "../psf"}
database -open ams_database -into ${AMS_RESULTS_DIR} -default

#
# Probe settings
#
probe -create -emptyok -database ams_database -flow {conditiondesvar.R0.1}

I can remove the conditional expression in the design variable and hard code R to a known value every time I run AMS. The problem is that I am trying to AMS simulate large design with more complex design variables created by other designers initially in Spectre env and it is really annoying with the little road blocks such as this one when transitioning to the AMS simulator.

TJ