Stats

  • Locked Locked
  • Replies 1
  • Subscribers 64
  • Views 13618
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

verilog-A file simulation value update to the design variable in ADE-L

Charanraj Mohan

Hey,

  I am using few iterations using the verilog-A file in spectre simulation. I have a design variable in ADE-L for a voltage pulse source written using pwlfile. I want that if my iteration in the code in verilog-A file succeeds my condition, the value I want should be used for a variable in the ADE-L. Is this possible ?  

Thanks in advance

  • Your question isn't that clear. Are you saying that you want your Verilog-A to calculate a value and then use that as a design variable in a subsequent simulation? If so, this can be done using ADE XL using calcVal to pass a measured output from one test to another - but before explaining that in more detail, I'd like you to clarify your question in case I've completely misinterpreted what you're asking...

    Regards,

    Andrew

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.