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controlling mismatch & other related queries.

Charanraj Mohan

Hello,

 I have few queries related to mismatch-

1. In my understanding if we select 'mismatch' in MC simulation, it means comparing electrical parameters between identical devices on a single wafer. It is the statistical variation due to differences in local doping, patterning & other manufacturing variables, which results in difference in device performance. Where as, on the other hand, when we select 'process' in MC simulation it is the same statistical variation, but it is the variation of devices in different wafers (can run 5 simulations if there is same circuit in 5 different wafers to get an estimate). And when I choose 'both', this gives an estimate of statistical variation of both identical devices on wafer & wafer-to-wafer variations. Am I right in all above views ? Plz correct me if am wrong.

2. In current mode circuits (like a basic current mirror or even a differential pair) one can keep the mismatch less by avoiding minimum length (CD control or reverse short-length effect) of the MOSFETs, using specific matching structures in the layout like using common-centroid (quad) layouts, inter-digitized scheme or even using square shaped MOSFETs (having W=L & connecting them in parallel, if W>L), have same orientation, have current flow in same direction, avoid metal covering on matched-transistors, etc. Is there any technique to keep mismatch low in generic CMOS circuits ? Also, Is there any other technique where one can reduce mismatch in MOSFETs that work in saturation, sub-threshold & linear region, as I am interested to know mismatch-reduction by MOSFET's operating region-wise, if it relates ? 

3. Specifically for controlling mismatch in circuits that handles low current (says in nA or pA) if there is any good book/reference, plz recommend. (Ignore if you know only the generic layout design books)

Thanks in advance Slight smile

Parents

  • Some attempts at answers:

    1. Yes, although the variation probably isn't "the same statistical variation". The standard deviation is likely to be different for mismatch and process variation.
    2. The approaches that you describe are not just for current mode circuits; it's any time you need the behaviour of the devices to be as consistent as possible. I'm not sure there are any different techniques that you'd apply just because the device is in a different region. Note, I should point out that mismatch analysis in Monte Carlo is really to analyse the remaining random variation and is not about the variation caused by poor layout matching practices. Of course, if you're looking at a circuit that is sensitive to mismatch of certain devices then the ones you need to focus on are likely to be the same as those which show up as significant contributors based on their random variation.
    3. Can't answer this, sorry.

    Regards,

    Andrew.

Reply

  • Some attempts at answers:

    1. Yes, although the variation probably isn't "the same statistical variation". The standard deviation is likely to be different for mismatch and process variation.
    2. The approaches that you describe are not just for current mode circuits; it's any time you need the behaviour of the devices to be as consistent as possible. I'm not sure there are any different techniques that you'd apply just because the device is in a different region. Note, I should point out that mismatch analysis in Monte Carlo is really to analyse the remaining random variation and is not about the variation caused by poor layout matching practices. Of course, if you're looking at a circuit that is sensitive to mismatch of certain devices then the ones you need to focus on are likely to be the same as those which show up as significant contributors based on their random variation.
    3. Can't answer this, sorry.

    Regards,

    Andrew.

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