VCD FIle Input to ADE-L

Al,

Yes, you can use spectre. This is documented in the Spectre® Circuit Simulator and Accelerated Parallel Simulator User Guide in the Verilog Value Change Dump Stimuli appendix (appendix E in the version I was looking at).

You have to manually write the signal information file - this is documented in the appendix I mentioned. It has to be manually written because it describes things like the rise and fall times, the high and low values and so on - this is information that doesn't exist in the digital simulation world.

Where are the warnings you  are talking about? Are these warnings in the schematic editor when you check and save (you weren't very clear about what the warnings were related to). If it's about a net that isn't connected in the schematic - they don't really matter. You could just add a "noConn" component from the basic library to stop the warnings if they bother you. Unless of course you're talking about something else - I'm guessing.

Regards,

Andrew.

Andrew,

I did create my signal info file and had to fix the scope and upscope commands since I am trying to use the signals at the top level. 

The warnings are, yes, floating nets which are named the same as my signals in the .vcd file. I used an alias in the signal info file to give them the same name. The simulation has no error but it doesn't show the correct output. 

1.) How do you plot the signals from the .vcd file using ADE-L or spectre?

2.) How do I know that the signal name in the .vcd file gets fed properly into the net in the analog schematic?

Here is a snapshot of my .vcd file:

$comment
TOOL: simvision(64) 14.10-p001
$end

$date
Jan 24, 2018 17:56:11
$end

$timescale
1ps
$end

$var wire 1 # cleara $end
$var wire 1 $ clearb $end
$var wire 1 % conna $end
$var wire 1 & connb $end

$enddefinitions $end
#1066137000
$dumpvars
0#
0$
0%
0&
$end
#1066803200

and my .signal file 

.hier 0
.alias cleara clear33a
.alias clearb clear33b
.alias conna conn33a
.alias connb conn33b
.out cleara clearb conna connb 
.trise 100 cleara clearb conna connb 
.tfall 100 cleara clearb conna connb
.voh 1.8
.vol 0.0

Thanks again Andrew! 

Al

Al,

You need to use .in rather than .out. The purpose of .out is for checking real signals in  your circuit against those in the VCD file - whereas you want the signals to be input stimulus.

Regards,

Andrew.