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unable to simulate this veriloga code in cadence

noob1

To the respected form members I am noob to this I have a Veriloga code with me but I am facing parsing error with it The code is genuine and i want to know where it get wrong thank you.

code:

https://drive.google.com/open?id=0BxdIdGj7u4DWeTdQUUlpOW5ZUUJpLWRKaTRPSGRLemVTZjNN

this is the google link for the

  • First you should read the Forum Guidelines. You didn't say where you were getting these parser errors (which tools, which versions) or what the errors are.

    I tried reading the file in spectre. There are two issues:

    1. The file has strange line endings. Normally on Windows you'd have "CRLF" (carriage return+line feed) or on Linux you'd have "LF" (line feed only). This has Carriage return only - and that seems to trouble the spectre parser (it troubles lots of things to be honest). I fixed that by doing (in Linux):
        mv ucsb_2dfet.va ucsb_2dfet_orig.va
        cat ucsb_2dfet_orig.va | tr '\r' '\n' > ucsb_2dfet.va
    2. Then it fails with this:

      Error found by spectre during AHDL read-in.
        ERROR (VACOMP-2259): "modulel<<--? tmdfet(S,D,Gt,Gb); "
          "ucsb_2dfet.va", line 5: syntax error.
        ERROR (VACOMP-1814): Maximum allowable errors exceeded. Exiting AHDL
          compilation....

      That's because at the beginning it starts with "modulel" and it should be "module". If I fix that, all is OK (well, it compiles and simulates - I can't vouch for whether the model works OK or not).

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    Thanks sir,

    You are right about the EOL . IT has been helpful.

    Regards,

    Hafi.

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