Verilog A ADC design

Well, the first problem is that with an input signal of 4GHz and a clock frequency of 800MHz, your signal is undersampled (i.e. above Nyquist) and so you'd expect a DC output since the input signal is an exact multiple of the clock - each sample will end up at the same phase point in the sine wave. The graph image shows what looks more like a ramp rather than a sine wave - and that ramp is effectively half of a 10MHz triangle wave.

However, I suspect if it's producing all zeros, you've not set the threshold for the clock properly. You didn't say what signal levels you've used or what parameters you set on the ADC. In order to make it easier to see, I just did this from a spectre netlist, but here's what I used to test it (the code above is in forum42.va):

//

parameters FREQ=40M CYCLES=1
Vclk (clk 0) vsource type=pulse val0=0 val1=1.8 period=1.25n rise=1p fall=1p width=1.25n/2
Vsin (sin 0) vsource type=sine freq=FREQ ampl=0.25 dc=0.5
Iadc (sin clk d9 d8 d7 d6 d5 d4 d3 d2 d1 d0) adc_8bit vth=0.9

ahdl_include "forum42.va"
tran tran stop=1/FREQ*CYCLES

The simulation was just run with "spectre forum42.scs" and then the results looked at in "viva". I could then easily change the FREQ - here it's 40MHz, but if you change it to 4G you'll see a flat output signal. The bus at the bottom was produced with ViVA's Measurement->Analog to Digital and then the resulting bus was converted back into analog using Measurement->Analog to Digital and is overlayed over the input sine wave:

If you had a pulse source for the clock but the input threshold (vth on the ADC) was left at default, it's probably just not switching (I get all zeros), but even if I use a 4GHz sine wave and have a sensible vth I just get a (as expected) constant output from the ADC (not all zeros, but constant nevertheless).

If you don't understand about Nyquist, then I suggest you speak to your supervisor/tutor (I'm assuming you're a University student).

Regards,

Andrew.

Thanks Andrew for your descriptive reply.

To be very specific I am using this ADC in the front end for data acquisition in Compressive sampling. For my final year thesis ( I am an undergrad student in ECE stream)  I am working in this field. Can you please try to go through this thesis which I am trying to implement? In the conclusion section, it has mentioned that the clock input should of 800MHz and the system operates at 4Ghz. The output of the integrator is fed to the ADC (10 bit).

After generating the symbol in Cadence I just tried to check the performance of the ADC by giving those inputs of 4Ghz sine wave with 0.25 vmax and 0.25 vmin ,zero DC value. The clk values was set at 1(high) and 0(low). I had used vpulse source for clock and vsin block for the sine wave. The parameters of the ADC was left unchanged and the same code was run. 

Do I need to change anything in the code, any parameters of the ADC?

Yes, maybe I have not adhered to the Nyquist criteria for the ADC.

Given that I'm not realistically going to study a 60-odd page thesis to answer a question on the forums (you have to do something for your degree!) I merely quickly scanned it. The system is a sub-Nyquist undersampling system - but it's using a PRBS source, not a sinusoidal input. A sinusoidal signal which is coperiodic with the clock is going to be sampled with the same value at each clock edge, so you're going to get a constant output. In your case though, the first problem is that you haven't set the parameters of the ADC. If you have the  signals as you've described, then you should (on the edit properties form for the ADC) enter (first pick the CDF filter to be veriloga so that it shows the parameters), then fill in the vmax, vmin (to control the maximum range of your input signal so that the ADC uses the full range), and vth to be the mid-point of your logic signals (so 0.5V here). I also set "one" to be 1 so that the digital outputs of the ADC have the same voltage range as your clock:

That will at least make sure that the ADC is clocked (it won't be otherwise) and that the range of the signals that the ADC is converting matches your input signal. The next problem is that your input signal is co-periodic with the clock. To illustrate this, I've plotted the clock signal you describe together with the 4GHz sine wave, and put vertical markers at the 0.5V rising crossing points of the clock:

As you can see, the sample points are identical so the ADC would convert the 3.14mV for each sample - it will be constant. Hardly surprising given they're co-periodic. Presumably (without reading the thesis), the input signal is not periodic (if it's a PRBS), and so you'd end up getting a varying output, which presumably is useful in this circuit.

Just to explain what happens when you apply a frequency above Nyquist, I simulated with the same settings you did but with a 4.1GHz sine input. Here's what I get:

Note that the frequency at the bottom (this is the re-constructed digital output of the ADC) has a sine wave at 100MHz - which is the "beat" frequency of the 4.1GHz input signal and the 800MHz clock. This is the aliasing effect you'd expect - but with a 4GHz input signal, you'll end up with a 0Hz (DC) "beat" frequency. I think in the situation in the thesis, the input signal is non-periodic, so you'd still get some output though.

The picture on Page 40 of the thesis (which you posted above) is just (as I said) showing the result of a ramp over 50ns between vmin and vmax. It's not the result of a 4GHz sine wave input.

Regards,

Andrew.

Given that I'm not realistically going to study a 60-odd page thesis to answer a question on the forums (you have to do something for your degree!) I merely quickly scanned it. The system is a sub-Nyquist undersampling system - but it's using a PRBS source, not a sinusoidal input. A sinusoidal signal which is coperiodic with the clock is going to be sampled with the same value at each clock edge, so you're going to get a constant output. In your case though, the first problem is that you haven't set the parameters of the ADC. If you have the  signals as you've described, then you should (on the edit properties form for the ADC) enter (first pick the CDF filter to be veriloga so that it shows the parameters), then fill in the vmax, vmin (to control the maximum range of your input signal so that the ADC uses the full range), and vth to be the mid-point of your logic signals (so 0.5V here). I also set "one" to be 1 so that the digital outputs of the ADC have the same voltage range as your clock:

That will at least make sure that the ADC is clocked (it won't be otherwise) and that the range of the signals that the ADC is converting matches your input signal. The next problem is that your input signal is co-periodic with the clock. To illustrate this, I've plotted the clock signal you describe together with the 4GHz sine wave, and put vertical markers at the 0.5V rising crossing points of the clock:

As you can see, the sample points are identical so the ADC would convert the 3.14mV for each sample - it will be constant. Hardly surprising given they're co-periodic. Presumably (without reading the thesis), the input signal is not periodic (if it's a PRBS), and so you'd end up getting a varying output, which presumably is useful in this circuit.

Just to explain what happens when you apply a frequency above Nyquist, I simulated with the same settings you did but with a 4.1GHz sine input. Here's what I get:

Note that the frequency at the bottom (this is the re-constructed digital output of the ADC) has a sine wave at 100MHz - which is the "beat" frequency of the 4.1GHz input signal and the 800MHz clock. This is the aliasing effect you'd expect - but with a 4GHz input signal, you'll end up with a 0Hz (DC) "beat" frequency. I think in the situation in the thesis, the input signal is non-periodic, so you'd still get some output though.

The picture on Page 40 of the thesis (which you posted above) is just (as I said) showing the result of a ramp over 50ns between vmin and vmax. It's not the result of a 4GHz sine wave input.

Regards,

Andrew.

Thanks, Sir. That solved the problem.

Can you say how did you create the 10-bit bus for the 10-bit output? I am facing some difficulty in doing that.

I selected the 10 signals d0 to d9 and then did (in the ViVA graph) Measurements->Analog to Digital. I specified the mid-value for the threshold, and made sure that the "Make Bus" was checked. If the bits are in the wrong order (MSB->LSB) then you can fix this by clicking on the Signal/Expr Names column heading to reverse the sort. You can control the radix and give a name for the bus - and then it adds the bus to the output.

Hopefully that's clear enough without me posting a picture of the form.

Regards,

Andrew.