possible to instantiate Verilog module in VerilogA?

Hi David,

Only verilogA or spice blocks can be instantiated in a hierarchical verilogA module, so you cannot instantiate a verilog module.

Regards,
Saloni

thanks Saloni,

looks like it. if I put in a VerilogA instance in, it'll see it in the hierarchy editor. it doesn't do the same thing if I instantiate a Verilog module (I do have connectLib available). 

anyway, thanks a lot,

David

thanks Saloni,

looks like it. if I put in a VerilogA instance in, it'll see it in the hierarchy editor. it doesn't do the same thing if I instantiate a Verilog module (I do have connectLib available). 

anyway, thanks a lot,

David

David,

You could put the VerilogA code in a VerilogAMS view, and then you should be able to instantiate Verilog (digital) within the block and simulate it in AMS.

The issue is that VerilogA is an analog-only subset of the VerilogAMS standard, and so it makes no sense to instantiate verilog within it, so that's not supported in the flow. 

Regards,

Andrew.

hi Andrew,

sounds like a good trick. And I am able to make the "config" happy which finds the verilog cell (say child) as instantiated inside VerilogAMS block(say parent cell). but when compiling, it still complains this child Verilog cell is referenced but not defined yet. 

    Error found by spectre in `parent', during circuit read-in.
    ERROR (SFE-23):
    "...parernt/verilogams/veriloga.va" 246:
    The instance `child' is referencing an undefined model or subcircuit,
    `child'. Either include the file containing the definition of
    `child', or define `child' before running the simulation.

some clue to make it work?

thanks a lot,

David

Hi David,

All you have there is a Verilog-A view where the view name is "verilogams". The view name can be whatever you like - it doesn't affect the type of the view. 

You need to create the view by setting the Type to "VerilogAMSText" on the File->New form in Virtuoso.

I can tell you've just created a veriloga view because the filename is still "veriloga.va". That is handled by the spectre engine and so it's assumed to be pure analog.

Regards,

Andrew.

hi Andrew, 

Mixed up around and yup I get it work now. thanks a lot.

David