table_model multi-column data file

Hi Olivier,

This got put into moderation because the system saw the repeated text and assumed it was spam. I moved it out of moderation, and then moved it to this forum instead as it's more appropriate for mixed-signal modelling.

I think what  you want is:

vy1=$table_model(vx,"forum48.txt","1L;1");
vy2=$table_model(vx,"forum48.txt","I,I,1L;1");
vy3=$table_model(vx,"forum48.txt","I,I,I,I,1L;1");

In the first case, you want the left most column as the independent variable, and then the next column after that as the dependent variable (the output). That's the ;1 bit which tells it that the first of the remaining columns is the dependent variable. For the subsequent outputs, you always want to ignore a pair of columns, and then use the odd columns as the independent variable, with the column straight after that as being the dependent variable.

I tweaked the numbers in  your table just so I could test that it was behaving as I was expecting - seems to work OK this way (if I've understood your requirement). Of course, I'm expecting that vx is the independent variable you're trying to look up in the table. Here's what I used for testing:

`include "disciplines.vams"
module forum48(op,ip);
output op;
input ip;
electrical op,ip;

real vx,vy1,vy2,vy3;
analog begin
  vx=V(ip);
  vy1=$table_model(vx,"forum48.txt","1L;1");
  vy2=$table_model(vx,"forum48.txt","I,I,1L;1");
  vy3=$table_model(vx,"forum48.txt","I,I,I,I,1L;1");
  V(op) <+ vy1;
end

endmodule

and then the netlist (I just tested with the above as a VerilogA model in forum48.va) with the netlist below as forum48.scs:

//

vramp (ramp 0) vsource type=pulse rise=1u val0=0 val1=3e-7
I1 (meas ramp) forum48

ahdl_include "forum48.va"

myopts options saveahdlvars=all
tran tran stop=1u

Regards,

Andrew.

Dear Andrew,

thank you very much for your answer. It works perfectly.

If I may, I'd like to ask you another question related to table_model. Do you know what is the algorithm behind this function ? I would like to know if the table model loads the entire table once or if it access the file everytime I ask for it ? I ask this because my simulation time is quite long compared to transistor level (spectre) simulation... The design is small, around 30 transistors (65nm). schematic level takes around 200ms, verilog-wreal with table 4s...

thank you for your answer.

OL

I don't know, is the simple answer. I suspect it's not read at each time point and is smarter than that (even if it was, I suspect it wouldn't have such a big impact). More likely it's some convergence challenge caused by your model - I can't really say though.

This is something that would be best handled through customer support so that it can be investigated more closely.

Regards,

Andrew.