Changing the number of input bits in a DAC and problem in ADE simulation

Virtuoso does not support parameterised bus pins and hence this makes doing this slightly trickier. The good news is that it's not impossible - you need to create PCells for the symbol and also the netlist.oa view within the veriloga view, and a netlist procedure so that spectre knows how to netlist the variable connectivity. I've been meaning to put together an example of how to do this for some time, so this gave me the excuse! Please find the code below (see the comments within). Note that you will need to change the VerilogA code slightly - it should be (note I reversed the bus order to be consistent with the pcell code too, as well as making the bus bits wide; previously it was bits+1 wide):

input [bits-1:0] in;
voltage out, clk;
voltage [bits-1:0] in;

Regards,

Andrew.

/* abGenericDAC.il

Author     A.D.Beckett
Group      Custom IC (UK), Cadence Design Systems Ltd.
Language   SKILL
Date       Jul 25, 2018 
Modified   
By         

SKILL code to support a veriloga model with a variable width
bus as input - in this case a DAC model. Works by creating
PCells and a netlist procedure to handle the varying connectivity.

First create a veriloga view with this content, and then call
abCreateGenericDACViews() (with appropriate arguments) to create the
symbol pcell, the pcell for the netlist.oa, and the CDF. Note that
the pins need to match between the veriloga and the pcell code (and
netlist procedure), and the parameters need to match the CDF in the
creation code below.

This file will also need to be loaded from the libInit.il within
the library containing the component so that the netlist procedure is
loaded when the library is first accessed in each session.

`include "constants.vams"
`include "disciplines.vams"

module genericDAC(out, in, clk);
parameter integer bits = 4;
parameter real fullscale = 1.8;
parameter real td = 0;
parameter real tt = 0;
parameter real vdd = 1.8;
parameter real thresh = 0.9;

output out;
input clk;
input [bits-1:0] in;
voltage out, clk;
voltage [bits-1:0] in;
real aout;
integer weight;
genvar i;

analog begin
    @(cross(V(clk) - thresh, 1) or initial_step) begin
        aout = 0;
        weight = 2;
        for(i = bits - 1; i>=0; i = i-1) begin
            if(V(in[i]) > thresh) begin
                aout = aout + fullscale/weight;
            end
            weight = weight*2;
        end
    end
    V(out) <+ transition(aout,td,tt);
end

endmodule

***************************************************

SCCS Info: @(#) abGenericDAC.il 07/26/18.14:25:22 1.2

*/

/********************************************************************
*                                                                   *
*     abCreateGenericDACViews(library @key (cell "genericDAC"))     *
*                                                                   *
*  Create the symbol pcell, the veriloga shadow pcell, and the CDF  *
*   for the genericDAC. This is to allow a variable width pin on    *
* the genericDAC model, which normally isn't supported in Virtuoso. *
*                                                                   *
********************************************************************/
procedure(abCreateGenericDACViews(library @key (cell "genericDAC"))
 let( (pcellId (view "symbol") (viewType "schematicSymbol")
        tempFile tempPort params)
    unless(ddGetObj(library)
        error("Couldn't open library %L" library)
    )

    when(ddGetObj(library cell "symbol")
        ddDeleteObj(ddGetObj(library cell "symbol"))
    )

    ;--------------------------------------------------------------------
    ; Create the symbol pcell
    ;--------------------------------------------------------------------
    pcellId=eval(`pcDefinePCell(
        list(ddGetObj(,library) ,cell ,view ,viewType)

        ;----------------------------------------------------------------
        ; Formal parameters
        ;----------------------------------------------------------------
        (
            (bits 4)
        )

        ;----------------------------------------------------------------
        ; Code itself
        ;----------------------------------------------------------------
        let(( cv netIn netClk 
            netOut figIn figClk figOut hp ps pl bw lh
            pxc label)

        cv = pcCellView

        ;----------------------------------------------------------------
        ; Various dimensions
        ;----------------------------------------------------------------
        ; half pin size
        hp=0.025
        ; pin spacing
        ps=0.125
        ; pin length
        pl=0.250
        ; box width
        bw=1.4375
        ; label height
        lh=0.0625
        ; param label x coord
        pxc=0.5

        ;----------------------------------------------------------------
        ; create the shapes - first the pins
        ;----------------------------------------------------------------
        figIn = dbCreateRect(cv list("pin" "drawing") list(-hp:-hp hp:hp)) 
        dbCreateLine(cv list("device" "drawing") list(0:0 pl:0))
        figClk = dbCreateRect(cv list("pin" "drawing") list(-hp:-ps-hp hp:-ps+hp))
        dbCreateLine(cv list("device" "drawing") list(0:-ps pl:-ps))
        figOut = dbCreateRect(cv list("pin" "drawing")
            list(2*pl+bw-hp:-hp 2*pl+bw+hp:hp)
        ) ; dbCreateRect
        dbCreateLine(cv list("device" "drawing") list(pl+bw:0 2*pl+bw:0))
        ;----------------------------------------------------------------
        ; Then the boxes
        ;----------------------------------------------------------------
        dbCreateRect(cv list("device" "drawing") list(pl:-2*ps pl+bw:ps))
        dbCreateRect(cv list("instance" "drawing") list(0:-2*ps 2*pl+bw:ps))

        ;----------------------------------------------------------------
        ; create the nets
        ;----------------------------------------------------------------
        netIn=dbMakeNet(cv sprintf(nil "in<%d:0>" bits-1))
        netClk=dbMakeNet(cv "clk")
        netOut=dbMakeNet(cv "out")
        ;----------------------------------------------------------------
        ; create the terminals
        ;----------------------------------------------------------------
        dbCreateTerm(netIn netIn~>name "input")
        dbCreateTerm(netClk netClk~>name "input")
        dbCreateTerm(netOut netOut~>name "output")
        ;----------------------------------------------------------------
        ; create the pins
        ;----------------------------------------------------------------
        dbCreatePin(netIn figIn)
        dbCreatePin(netClk figClk)
        dbCreatePin(netOut figOut)

        ;----------------------------------------------------------------
        ; Put some labels for the pins
        ;----------------------------------------------------------------
        dbCreateLabel(cv list("pin" "drawing") pl+ps/2:0
            netIn~>name "centerLeft" "R0" "stick" lh)
        dbCreateLabel(cv list("pin" "drawing") pl+ps/2:-ps
            netClk~>name "centerLeft" "R0" "stick" lh)
        dbCreateLabel(cv list("pin" "drawing") bw+pl-ps/2:0
            netOut~>name "centerRight" "R0" "stick" lh)

        ;----------------------------------------------------------------
        ; And other symbol labels
        ;----------------------------------------------------------------
        label=dbCreateLabel(cv list("annotate" "drawing7") bw+pl-ps/2:ps*1.5
            "cdsName()" "centerRight" "R0" "stick" lh)
        label~>labelType="ILLabel"
        label=dbCreateLabel(cv list("annotate" "drawing") pxc:0
            "cdsParam(1)" "centerLeft" "R0" "stick" lh)
        label~>labelType="ILLabel"
        label=dbCreateLabel(cv list("annotate" "drawing") pxc:-ps
            "cdsParam(2)" "centerLeft" "R0" "stick" lh)
        label~>labelType="ILLabel"

        dbSetConnCurrent(cv)
        t
        ) ; let
    ))
    dbSave(pcellId)
    dbClose(pcellId) 

    ;--------------------------------------------------------------------
    ; Create the pcell in the "shadow" database (netlist.oa) in the
    ; veriloga view. This is so the terminals match in the switch view.
    ; Can't use pcDefinePCell because that creates a "master" OA
    ; database, and this needs to be done as a non-master database (the
    ; master is the veriloga.va file). So this works by creating a file
    ; with the code in, and then using dbDefineProc to associate it with
    ; the cellView (see further down).
    ;--------------------------------------------------------------------
    tempFile=makeTempFileName("/tmp/pccode")
    tempPort=outfile(tempFile)
    pprint(
        'procedure(pcGenCell(cv "d")
            let((pcParams bits)
                pcParams=cv~>parameters
                bits=pcParams~>bits
                unless(fixp(bits) bits=4)
                let((netIn netClk netOut)
                    netIn=dbMakeNet(cv sprintf(nil "in<%d:0>" bits-1))
                    netClk=dbMakeNet(cv "clk") 
                    netOut=dbMakeNet(cv "out") 
                    dbCreateTerm(netIn netIn~>name "input")
                    dbCreateTerm(netClk netClk~>name "input") 
                    dbCreateTerm(netOut netOut~>name "output") 
                    ;----------------------------------------------------
                    ; this is to stop the instance being omitted
                    ; because there's no hierarchy
                    ;----------------------------------------------------
                    dbCreateProp(cv "nlAction" "string" "stop")
                    dbSetConnCurrent(cv)
                )
            ))
        tempPort
    )
    newline(tempPort)
    close(tempPort)

    ;--------------------------------------------------------------------
    ; Now create the non-master database (that's what the "wc" is for).
    ; Has to create the parameters hier prop and the pcell parameter
    ;--------------------------------------------------------------------
    pcellId=dbOpenCellViewByType(library cell "veriloga" "netlist" "wc")
    params = dbCreateHierProp(pcellId "parameters")
    dbCreateProp(params "bits" "int" 4)
    dbDefineProc(pcellId tempFile)
    dbSave(pcellId)
    dbClose(pcellId)
    deleteFile(tempFile)

;------------------------------------------------------------------------
; Now create the CDF
;------------------------------------------------------------------------

let( ( cellId cdfId )
    unless( cellId = ddGetObj( library cell )
        error( "Could not get cell %s." cell )
    )
    when( cdfId = cdfGetBaseCellCDF( cellId )
        cdfDeleteCDF( cdfId )
    )
    cdfId  = cdfCreateBaseCellCDF( cellId )

    ;;; Parameters
    cdfCreateParam( cdfId
        ?name           "bits"
        ?prompt         "bits"
        ?defValue       4
        ?type           "int"
        ?display        "t"
    )
    cdfCreateParam( cdfId
        ?name           "fullscale"
        ?prompt         "fullscale"
        ?defValue       "1.8"
        ?type           "string"
        ?display        "t"
        ?parseAsNumber  "yes"
        ?parseAsCEL     "yes"
    )
    cdfCreateParam( cdfId
        ?name           "td"
        ?prompt         "td"
        ?defValue       "0"
        ?type           "string"
        ?display        "t"
        ?parseAsNumber  "yes"
        ?parseAsCEL     "yes"
    )
    cdfCreateParam( cdfId
        ?name           "tt"
        ?prompt         "tt"
        ?defValue       "0"
        ?type           "string"
        ?display        "t"
        ?parseAsNumber  "yes"
        ?parseAsCEL     "yes"
    )
    cdfCreateParam( cdfId
        ?name           "vdd"
        ?prompt         "vdd"
        ?defValue       "1.8"
        ?type           "string"
        ?display        "t"
        ?parseAsNumber  "yes"
        ?parseAsCEL     "yes"
    )
    cdfCreateParam( cdfId
        ?name           "thresh"
        ?prompt         "thresh"
        ?defValue       "0.9"
        ?type           "string"
        ?display        "t"
        ?parseAsNumber  "yes"
        ?parseAsCEL     "yes"
    )

    ;;; Properties
    cdfId->formInitProc            = ""
    cdfId->doneProc                = ""
    cdfId->buttonFieldWidth        = 340
    cdfId->fieldHeight             = 35
    cdfId->fieldWidth              = 350
    cdfId->promptWidth             = 175
    ;--------------------------------------------------------------------
    ; note that this needs a netlist proc so that it can
    ; handle the variable number of pins
    ;--------------------------------------------------------------------
    cdfId->viewInfo                = '(nil veriloga (nil  moduleName "genericDAC"
namePrefix "ahdl" netlistProc abGenericDACNetlistProc stringParameterList
nil parameterList (bits fullscale td tt vdd thresh))
)
    cdfSaveCDF( cdfId )
)
 ) ; let
)

/****************************************************************
*                                                               *
*                abGenericDACNetlistProc(inst)                  *
*                                                               *
*  Netlist procedure to netlist the instance. Mostly standard   *
* other than the list of terminals which is constructuted based *
*                    on the bits parameter.                     *
*                                                               *
****************************************************************/
procedure(abGenericDACNetlistProc(inst)
    let((formatter netlister termList bits)
        formatter=nlGetFormatter(inst)
        netlister=nlGetNetlister(formatter)
        nlPrintInstComments(formatter inst)
        nlPrintIndentString(netlister)
        nlPrintInstName(formatter inst)
        ;----------------------------------------------------------------
        ; Output the correct terminal list
        ;----------------------------------------------------------------
        bits=atoi(nlGetParamStringValue(inst "bits"))
        nlPrintString(netlister " ( ")
        termList=`("out" ,@dbProduceMemName(sprintf(nil "in<%d:0>" bits-1))
            "clk")
        foreach(term termList
            nlPrintString(netlister nlGetTerminalSignalName(inst term) " ")
        )
        nlPrintString(netlister ") ")
        nlPrintModelName(formatter inst)
        nlPrintInstParameters(formatter inst)
        t
    )
)

Hi Andrew,

Actually I'm just beginner in Verilog A.

Thq for solution,I tired your code and with steps you mentioned it was easy and i was successful.

I just tired to implement this DAC module with my design but I'm not able to change the parameters such threshold.

The parameters much be changed both in Verilog A code and Skill code is that right ?

Dear Anushka,

Did you instantiate this symbol on a Virtuoso schematic? If so, you can change the parameters by doing a query of the symbol and change the defined parameters. For example, in Figure 1, I did a query of a veriloga ADC that has a parameter rise_fall_time. Note that its value is shown as 10e-12. If the cell were editable (this one happens to be read-only), one could change that value from 10e-12.

Shawn

Figure 1

Shawn,

Your example is a little odd, as it appears to not have any CDF parameters (normally creating the VerilogA would cause CDF parameters to get created - although you normally have to choose the "CDF Tools Filter" choice on the form to see them).

Anusha - perhaps you can show a screenshot of what the create instance or edit properties forms look like when instantiating or editing the instance of the genericDAC?

Regards,

Andrew

Hi Andrew,

Andrew Beckett said:

Your example is a little odd, as it appears to not have any CDF parameters (normally creating the VerilogA would cause CDF parameters to get created - although you normally have to choose the "CDF Tools Filter" choice on the form to see them).

You are correct. I did not include the option to show the CDF parameter. The updated Figure 1 details the CDF parameter when its view is enabled. Thank you for adding the more illustrative suggestion to the example!

Shawn

Figure 1 (updated to include CDF) illustrates the CDF parameter rise_fall_time

Hi Shawn,

Thank you that actually helped.

Hi Andrew,

This is how my edit properties form look like when I did query on VerilogA Instance.

Regards,

Anusha

Anusha,

So are you saying that it worked now that you are able to access the parameters?

Andrew

Andrew,

Ya it worked now. I was able to change the parameters.

Regards,

Anusha

Andrew,

Ya it worked now. I was able to change the parameters.

Regards,

Anusha

Dear Anusha,

Thank you for letting us know you have are able to change the parameters now - great! 

One note, as Andrew suggested, in the GUI that appears as a result of your symbol query, you have the "Use Tools Filter" view selected. This is a drop down menu and you can select "veriloga" as I did in the updated Figure 1 I posted.

Shawn