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Changing the number of input bits in a DAC and problem in ADE simulation

vasug7
vasug7 over 7 years ago

I am trying to design a generic N-bit DAC using variable input bits. Please take a look at a simple code snippet given below.

`include "constants.vams"
`include "disciplines.vams"

module DAC_va(out, in, clk);
parameter integer bits = 4;
parameter real fullscale = 1.8;
parameter real td = 0;
parameter real tt = 0;
parameter real vdd = 1.8;
parameter real thresh = 0.9;

output out;
input clk;
input [0:bits] in;
voltage out, clk;
voltage [0:bits] in;
real aout;
integer weight;
genvar i;

analog begin
@(cross(V(clk) - thresh, 1) or initial_step) begin
aout = 0;
weight = 2;
for(i = bits - 1; i>=0; i = i-1) begin
if(V(in[i]) > thresh) begin
aout = aout + fullscale/weight;
end
weight = weight*2;
end
end
V(out) <+ transition(aout,td,tt);
end
endmodule

The problem I am facing is that I don't know how to give multiple inputs to the in<> terminal of the DAC symbol in the schematic window.

I am new to working with Verilog A. Any help will be appreciated.

Thanks.

Virtuoso version - IC6.1.7-64b.500.15

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  • ShawnLogan
    ShawnLogan over 4 years ago in reply to Anusha Kumar

    Dear Anushka,

    Did you instantiate this symbol on a Virtuoso schematic? If so, you can change the parameters by doing a query of the symbol and change the defined parameters. For example, in Figure 1, I did a query of a veriloga ADC that has a parameter rise_fall_time. Note that its value is shown as 10e-12. If the cell were editable (this one happens to be read-only), one could change that value from 10e-12.

    Shawn

    Figure 1

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  • Andrew Beckett
    Andrew Beckett over 4 years ago in reply to ShawnLogan

    Shawn,

    Your example is a little odd, as it appears to not have any CDF parameters (normally creating the VerilogA would cause CDF parameters to get created - although you normally have to choose the "CDF Tools Filter" choice on the form to see them).

    Anusha - perhaps you can show a screenshot of what the create instance or edit properties forms look like when instantiating or editing the instance of the genericDAC?

    Regards,

    Andrew

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  • ShawnLogan
    ShawnLogan over 4 years ago in reply to Andrew Beckett

    Hi Andrew,

    Andrew Beckett said:
    Your example is a little odd, as it appears to not have any CDF parameters (normally creating the VerilogA would cause CDF parameters to get created - although you normally have to choose the "CDF Tools Filter" choice on the form to see them).

    You are correct. I did not include the option to show the CDF parameter. The updated Figure 1 details the CDF parameter when its view is enabled. Thank you for adding the more illustrative suggestion to the example!

    Shawn

    Figure 1 (updated to include CDF) illustrates the CDF parameter rise_fall_time

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  • Anusha Kumar
    Anusha Kumar over 4 years ago in reply to ShawnLogan

    Hi Shawn,

    Thank you that actually helped.

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  • Anusha Kumar
    Anusha Kumar over 4 years ago in reply to Andrew Beckett

    Hi Andrew,

    This is how my edit properties form look like when I did query on VerilogA Instance.

    Regards,

    Anusha

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  • Andrew Beckett
    Andrew Beckett over 4 years ago in reply to Anusha Kumar

    Anusha,

    So are you saying that it worked now that you are able to access the parameters?

    Andrew

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  • Anusha Kumar
    Anusha Kumar over 4 years ago in reply to Andrew Beckett

    Andrew,

    Ya it worked now. I was able to change the parameters.

    Regards,

    Anusha

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  • ShawnLogan
    ShawnLogan over 4 years ago in reply to Anusha Kumar

    Dear Anusha,

    Thank you for letting us know you have are able to change the parameters now - great! 

    One note, as Andrew suggested, in the GUI that appears as a result of your symbol query, you have the "Use Tools Filter" view selected. This is a drop down menu and you can select "veriloga" as I did in the updated Figure 1 I posted.

    Shawn

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