Unbound pins after LVS of a Innovus implemented instance

Hello all,

I've implemented a digital block in Innovus and I need to simulate it in an analog environment with AMS, so I imported the layout in Virtuoso (6.1.7) to get the analog_extracted view. I also imported the verilog netlist and converted it into a schematic via File->Import->Verilog on Virtuoso, to perform the LVS with Assura.

However, although I got no warnings or errors from Innovus, when I try to perform the LVS there are two unbound pins, vdd! and gnd!. Consequently, I also can't get the analog extracted view vith Quantus QRC because it can't find the gnd! net (seems like it doesn't exist), with the following error:

ERROR (FINDCAP-88016): cap ground signal 'gnd!' cannot be found.ERROR (FINDCAP-88016): cap ground signal 'gnd!' cannot be found.Check if net 'gnd!' exists in design and has the correct ?netNameSpace (schematic, layout) specified in RSF.

On Virtuoso Layout XL I can correctly see the names of the vdd! and gnd! nets, and also the connectivity of the metal paths that make the power ring seems ok, so thinking that the pins were simply missing I tried to create labels and then perform the command Tools->Create pins from labels, but the resulting created objects seem to be of type "Shape" instead of type "Pin" and are still not found during LVS.

I still don't know if the problem is during the Innovus flow or maybe there are some missing steps in the transition between Innovus and Virtuoso.

Any help or ideas are appreciated,

Thanks

Stefano