display analog signal voltage in VerilogAMS

hello exports,

wonder if I can find some help here. 

I want to display the analog signal's voltage at digital clock edge in VerilogAMS code. the compiler keeps telling me this hierarchical signal access is illegal. is there a way to achieve this? the hierarchy path is definitely right as it can compile if I remove "V()" although I don't get the right voltage answer. 

                 ncelab: *E,ILLSARG (..../verilogams/verilog.vams,735|52): Illegal argument for signal access function [4.3(AMSLRM)].

module testbench

   always @(negedge clk ) begin

   ...
      $display("====  %g  ", V(top.sub.leaf) );
   ...
   end

   analog begin 

   ...

   end

endmodule

regards,

David