Differences in resistor noise Verilog-A model

I split this into a separate post because it broke the Forum Guidelines by being about a different topic (yes, both questions were on Verilog-A, but that's really where the similarity ended; putting multiple different questions in the same thread makes it harder for somebody to identify if they have a similar issue). 

The root cause is that you cannot have both a current and voltage source on the same branch in Verilog-A. Spectre gives a clear warning:

WARNING (VACOMP-1117): "forum51d.va", line 9: Ignoring the contribution
statement on line 9 which contributes either a potential to a flow
source or a flow to a potential source. The value retention guidelines
in the Verilog-AMS LRM state that a branch can have either a flow
contribution or a potential contribution but not both.

In my case forum51d was your fourth code, and line 9 was this:

V(p, n) <+ I(p,n) * R;

Because this was omitted, the resistor was open circuit (the average current through the white_noise current source line would be 0), and so there was a conductance of 1e-12 added across the resistor to provide a path to ground.

What this means is that the voltage across the resistor would be the noise current through that 1TOhm gmin resistor (the 1e-12 conductance), which gives you a voltage of:

sqrt(4*1.38064852e-23*300.15/5000)*1e12 = 1.820773V

converting that to V^2/Hz gives 3.315213V - essentially what you got.

The reason why the other way around (Code 2) doesn't have this problem is because spectre omits the current source (so it won't behave as a resistor), but it's directly a voltage source (so closed circuit).

So the root cause is the illegal Verilog-A construct of having both voltage and current source contributions at the same time on the same branch.

Regards,

Andrew.

Hi Andrew,

Really appreciate your reply.

It seems obvious that we should check the warning before going to the result.

But I don't see any warning about the ignorance of contribution statement in my output log.

Is that an option in spectre to display the warning or the log is in a certain directory?

Thank you so much for answering!

This is probably because the model has been compiled in a previous run, and the warnings only appear during VerilogA compilation.

You could go into the netlist dir and delete the input.ahdlsimDB dir, or you could enable the "AHDL Linter" (which in ADE can be found on the Simulation->Options->Analog form, Miscellaneous Tab, near the bottom). If you can't find it there, you can go to Setup->Environment and in the userCmdLineOptions you can enter "-ahdllint" .

This will force it to recompile, and the messages will be in the spectre output log.

Regards,

Andrew.

I go to ADE -> Simulation -> Option -> Analog -> Miscellaneous -> AHDL LINTER OPTIONS (APS ONLY) -> Linter check -> on

The warning messages now appear in the spectre output log.

Thank you very much!

The messages would also appear if you change the VerilogA view in any way (without having to turn on the linter) - it's just the fact that it's been compiled already that meant that the messages are not repeated on each run.

Anyway, glad you can see them now.

Regards,

Andrew.