VerilogA Out-of-Module access top level nets?

Hi,

I want to probe some top level signals in my testbench.   

I have a veriloga signal generator which creates a time varying waveform and I only want to capture signals during specific periods of this pattern,  so I need to capture the signals within this block.

I know I can add input pins and then deal with the signals that way,  but just out of interest (laziness?) I wanted to capture these signals directly from within the verilogA module.

All the examples show an out-of-module reference to another (sibling) instance, eg,

module x_siggen(....)

localparam string probethis="I1.signal";

analog begin

trackthis = V(probethis);

end

endmodule

etc.

How do I access a signal at the top level ?

If I simply use probethis = "topsignal" the editor parser fails with...

ERR516 [149:10]: 'probethis' is not an analog node or branch.

Is there some syntax to access the top level as well ?