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Using systemVerilog files with AMS simulator

forXTer

I am having some trouble running a mixed signal simulation that references systemVerilog files. Typically what I do is set the digital block view to symbol in the hierarchy editor. I then include a file in AMS Options > Option files that has all of the .v/.sv files needed for the digital block. Running at this point will give syntax errors in the .sv file because the simulator does not know how to handle certain systemVerilog constructs. I can solve this by adding -sv under additional arguments. When I do that it then says disciplines.vams cannot be found and I get the following set of errors for each instance of a vsource.

vsource #(.type("dc")) IMess (\VDDP! , net09);
ncvlog: *E,EXPIDN (./netlist.vams,21273|14): expecting an identifier [7.2.3(AMSLRM)].


vsource #(.type("dc")) IMess (\VDDP! , net09);
ncvlog: *E,EXPLPA (./netlist.vams,21273|14): expecting a left parenthesis ('(') [7.2.3(AMSLRM)].


vsource #(.type("dc")) IMess (\VDDP! , net09);
ncvlog: *E,ILLPRI (./netlist.vams,21273|14): illegal expression primary [4.2(IEEE)].

I have used this same flow successfully in the past so I am not sure what is going wrong.

Parents

  • Just to follow up on this..I tracked this down to one of the IP files being a .v when it should have been .sv. When running purely verilog simulations the -sv switch was used so everything worked. This only became an issue when running a full chip AMS sim without the -sv switch.

    What I still don't understand is why the -sv switch breaks the AMS sim. From what I can find -sv just makes .v files compile as .sv. It seems like it changes everything (including .vams) to systemverilog and then has issues interpreting files that are not actually .v/.sv.

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  • Just to follow up on this..I tracked this down to one of the IP files being a .v when it should have been .sv. When running purely verilog simulations the -sv switch was used so everything worked. This only became an issue when running a full chip AMS sim without the -sv switch.

    What I still don't understand is why the -sv switch breaks the AMS sim. From what I can find -sv just makes .v files compile as .sv. It seems like it changes everything (including .vams) to systemverilog and then has issues interpreting files that are not actually .v/.sv.

Children
  • in reply to forXTer

    The reason why -sv breaks things is because the meaning of -sv (from "irun -helpall") is:

    -sv Force SystemVerilog compilation

    This means it forces system verilog compilation for all files and doesn't use the suffix info. So that means it would treat Verilog AMS as SystemVerilog, which it isn't, so it will break.

    Regards,

    Andrew.

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