Reading values from struct at the input of SystemVerilog model using AMS simulator.

Hello everybody,

I have problem with simulating two SystemVerilog models using AMS simulator (AMS Unified Netlister with xrun) in Cadence Virtuoso - schematic. I have placed two cells in schematic, GB and SEQ, as you can see at the image.

Goal of the simulation is to pass struct of real numbers from one cell to another via net test_pin.

Here is code of GB cell, which generates signal test_pin:

module IPC6319 (    BIAS_SSIP_IBIAS, BIAS_SSIP_IREF, ATB_BIAS_INTF, IO_BIAS_EXTRES[0],
                IO_BIAS_EXTRES[1], IO_BIAS_VREF_EXT, AVDD_BIAS, AVSS_BIAS, REG_BIAS_BGRTRIM,
                REG_BIAS_PWD_N, REG_BIAS_SSIP_PWD_N, REG_BIAS_TST, SUB_BIAS, test_pin);

  input AVSS_BIAS;
  input AVDD_BIAS;
  input SUB_BIAS;
  input [3:0] REG_BIAS_TST;
  input [7:0] REG_BIAS_BGRTRIM;
  input REG_BIAS_PWD_N;
  input [19:0] REG_BIAS_SSIP_PWD_N;
  output [19:0] BIAS_SSIP_IBIAS;
  output [19:0] BIAS_SSIP_IREF;
  inout [3:0] ATB_BIAS_INTF;
  inout [1:0] IO_BIAS_EXTRES;
  inout IO_BIAS_VREF_EXT;

  logic REG_BIAS_PWD_N;
  output test_pin;

  struct {
    real V = 1;
    real I = 1e-3;
    real R = 50;
  } test_pin;

endmodule

Here is a code for SEQ cell, which reads the test_pin signal:

module IPC6319_sequencer (REG_BIAS_TST, REG_BIAS_BGRTRIM, REG_BIAS_SSIP_PWD_N, REG_BIAS_PWD_N,
                        ATB_BIAS_INTF, BIAS_SSIP_IBIAS, BIAS_SSIP_IREF, IO_BIAS_VREF_EXT, test_pin);

  output [3:0]  REG_BIAS_TST;
  output [7:0]  REG_BIAS_BGRTRIM;
  output [19:0] REG_BIAS_SSIP_PWD_N;
  output        REG_BIAS_PWD_N;
  input [3:0]   ATB_BIAS_INTF;
  input [19:0]  BIAS_SSIP_IBIAS;
  input [19:0]  BIAS_SSIP_IREF;
  inout         IO_BIAS_VREF_EXT;
  logic [19:0] REG_BIAS_SSIP_PWD_N;
  logic        REG_BIAS_PWD_N;
  logic [7:0]  REG_BIAS_BGRTRIM;
  logic [3:0]  REG_BIAS_TST;

  int i = 0;
  real aaa;

input test_pin;

struct {
     real V;
     real I;
     real R;
} test_pin;

assign aaa = test_pin.V;

endmodule

After extracting I do not get any error. But simulation fails because of error:

xmelab: *E,TYCMPAT (./netlist.vams,38|41): port or terminal connection type check failed (expecting datatype compatible with 'anonymous unpacked structure' but found 'unpacked structure' instead).

This example of creating the same struct in SEQ and assigning test_pin.V to aaa is only one of the many which I tried.

I do not know how to work with test_pin struct. For example, i would like to assign value of V to some  other real variable or some work with this values from the test_pin struct.

Is it possible to do it like that?