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Plotting a digital bus as an analog signal

mwb1

Hi, I've created a DDS using an digital, encounter based flow and brought it into virtuoso as a Verilog block. I'm simulating it with spectre-XPS and the output is 6 bits "output<5:0>". In Viva, I use "create digital bus" to create a digital bus from the analog output signals and things look good. However, it would be easier for me to verify the functionality of the DDS by actually looking at the sinusoidal output. Essentially, my question is, is there a good way to look at the output as "output-code vs. time"? I've search and tried out all sorts of things but I can't seem to figure it out. I tried using dac_8bit_ideal from ahdlLib but it doesn't seem to work at all. I've tried a few things out in the calculator as well but to no avail. 

There has to be an easy way to do this right? I mean, how else would you verify operation of an ADC? 

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  • You can do this easily in ViVA. If your bus bits were analog in the first place, you can then create a digital bus from this using Measurements->Analog to Digital. Then select that bus and convert it back to Analog using Measurements->Digital to Analog - making sure you pick the options to have Bus output as Voltage. For example, I created a bus, mybus, from the analog bits at the top, and then the signal at the bottom is that bus converted back to a voltage:

  • in reply to Andrew Beckett

    Thanks Andrew. Unfortunately, I tried that and all I get is a blank plot. Im using IC6.1.6, do I need to use IC6.1.7?

    Matt 

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  • in reply to mwb1

    Hi Matt,

    I've not used IC616 in detail for a while (since that's two major releases ago) and can't remember whether there was an issue. Is there a good reason why you have to use such an old release? I can only imagine that this was a bug that was fixed (I vaguely recall there being an issue with converting a waveform to digital and then back to analog again - it didn't keep the overall expression correctly).

    Andrew

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