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Weird voltage level in verilogA simulation

hafiz2431

Hi,

I'm trying to calibrate a driver against a termination. Algorithm => sweep input code (clk_out[5:0]), check voltage at termination and lock the code (pu_code[5:0]) once the desired value is attained.

The code locked at the desired value (>=0.2) but the voltage levels at pu_code[5:0] are having some weird values (e.g. 0.9V, 0.462V) though logic hi is 0.8V (see the figure attached).

Can anybody explain the reason behind this?

Your assistance is appreciated.

Regards,

Hafiz

  • Here's the code for the calibration block:

    module nnbank_calib (
       clk_in,
       clk_out,
       midvtt,
       ack,
       pu_code
                       );
           
    input       clk_in;
    electrical      clk_in;
    output [5:0]  clk_out;
    electrical [5:0] clk_out;
    input    midvtt;
    electrical   midvtt;
    output    ack;
    electrical   ack;
    output [5:0]  pu_code;
    electrical [5:0] pu_code;
     
    parameter real  vth=0.4,
                    vol=0,
                    voh=0.8;
    parameter real trf=1p; 
        
    integer count2,n2,count4,n4,count8,n8,count16,n16,count32,n32, countlock;           

    analog begin
    @(initial_step("tran")) begin
    count2=-1;
    count4=-1;
    count8=-1;
    count16=-1;
    count32=-1;
    countlock = 0;
    end
    @(cross(V(clk_in) -vth,-1)) begin
        count2 = count2+1;
        if (count2 >= 2)
         count2 = 0;
         n2 = (2*count2 >= 2);
       
        count4 = count4+1;
        if (count4 >= 4)
         count4 = 0;
         n4 = (2*count4 >= 4);
     count8 = count8+1;
        if (count8 >= 8)
         count8 = 0;
         n8 = (2*count8 >= 8);
     count16 = count16+1;
        if (count16 >= 16)
         count16 = 0;
         n16 = (2*count16 >= 16);
     count32 = count32+1;
        if (count32 >= 32)
         count32 = 0;
         n32 = (2*count32 >= 32);
    end
    V(clk_out[0]) <+ V(clk_in);
    V(clk_out[1]) <+ transition (n2 ? voh : vol, 0, trf);
    V(clk_out[2]) <+ transition (n4 ? voh : vol, 0, trf);
    V(clk_out[3]) <+ transition (n8 ? voh : vol, 0, trf);
    V(clk_out[4]) <+ transition (n16 ? voh : vol, 0, trf);
    V(clk_out[5]) <+ transition (n32 ? voh : vol, 0, trf);

    @(cross(V(clk_in) -vth,0)) begin
        if (V(midvtt) >= 0.2) begin
      countlock = countlock+1;
      if (countlock == 1) begin
          V(pu_code[0]) <+ V(clk_out[0]);
          V(pu_code[1]) <+ V(clk_out[1]);
          V(pu_code[2]) <+ V(clk_out[2]);
          V(pu_code[3]) <+ V(clk_out[3]);
          V(pu_code[4]) <+ V(clk_out[4]);
          V(pu_code[5]) <+ V(clk_out[5]);
          V(ack)   <+ voh;  
      end
       end else begin
          V(pu_code[0]) <+ vol;
          V(pu_code[1]) <+ vol;
          V(pu_code[2]) <+ vol;
          V(pu_code[3]) <+ vol;
          V(pu_code[4]) <+ vol;
          V(pu_code[5]) <+ vol;
          V(ack)   <+ vol;
       end
     end
    end
    endmodule

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