Backgroud: Mixed Signal block, with most implementation in Virtuoso, small controller block from digital.
Problem: I have a top level post layout netlist with power and group pins from innovus. I want to use CDL file to define my gates in AMS simulator. Is that possible?
The reason behind is, I want to use Spectre/APS to calculate my module power and delay for my block. Since pointing to verilog module my block behaves as ideal (no delay or power).
I am aware of the fact that CDL is ment for LVS purpose only, but my understanding is if there is transistor level description I could use it.
Please let me know if it this possible,if so where should I specified?
I tried to specify it under setup --> simulation Files --> Definition files. It doesn't work.
I also tried with generating cdl for my controller verilog file and including it as "Specify SPICE source File" in config view. But in that case, my netlist failed due to bus signal in my testbench [this method works well if I have only non-bus signals, and I am able to see delay/power consumption from the block]
Please let me know if any more details required. Please let me know if there is any other method for the same.
Thank you in advance.