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VHDL view to use in heirarchy editor

riahm

Hello, I am very new to mixed signal simulation using cadence virtuoso. I want to simulate a design which includes an ADC(analog)  and a digital logic. The digital part of the design includes blocks written in verilog as well as VHDL.

I created a config view and imported all the digital design files. I use functional view for the verilog files but not sure which view to use for VHDL as these files are listed as behav and entitiy views. 

Also virtuoso does not list the heirarchy  for VHDL part of the design although it looks fine for verilog top level block.

regards,

Parents

  • You should just pick the architecture (which corresponds to a view in Virtuoso) that you want in the hierarchy editor. If there is hierarchy underneath that, you should be able to select that too.

    How did you import the VHDL code? Which simulator sub-version (irun -version) and IC sub-version (Help->About in any of the Virtuoso windows) are you using?

    Andrew

  • in reply to Andrew Beckett

    Hi Andrew,

    thanks for the reply. Sorry I forgot to mention tool version. I am using (xrun(64) 18.03-s010 ) and (IC6.1.8-64b.83)

    The VHDL design I am trying to simulate has only one architecture. This architecure has a name behave. After importing VHDL module I see three views in the list.

    • symbol
    • entity
    • behave(architecture)

    I chose behave but not able to see heirarchy in the config view which I have defined for the simulation. I import using virtuoso>file>import>VHDL import

Reply
  • in reply to Andrew Beckett

    Hi Andrew,

    thanks for the reply. Sorry I forgot to mention tool version. I am using (xrun(64) 18.03-s010 ) and (IC6.1.8-64b.83)

    The VHDL design I am trying to simulate has only one architecture. This architecure has a name behave. After importing VHDL module I see three views in the list.

    • symbol
    • entity
    • behave(architecture)

    I chose behave but not able to see heirarchy in the config view which I have defined for the simulation. I import using virtuoso>file>import>VHDL import

Children
  • in reply to riahm

    You still didn't say how you imported the code...

  • in reply to Andrew Beckett

    I mentioned it in the last line.

    I import the code using VHDL import form which you can pull from the file menu in virtuoso window. I have attached a screenshot. Thank you for your help

  • in reply to riahm

    My apologies - you edited the post after the email notifier was sent (I believe) because the statement about how you imported wasn't  in the email, and I didn't notice it on the web page when I answered.

    I just tried with an example, and it's working for me. Are there any errors in the CIW when you open the hierarchy editor? Can you show what the hierarchy editor looks like? 

    To be honest, this is best dealt with via customer support, as seeing your data would really help.

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    Hi Andrew,

    Yes I edited the post. no worries.

    Yes I get the following warning and error in CDS.log:

    *WARNING* Object: DCS_CONTROLLER_DIG.dut(behave) pc.db cannot be opened

    ERROR (HED-1073): Failed to open parent-child database for cellview (DCS_CONTROLLER_DIG dut behave).

    Also, I see in the Hierarchy editor that this block is colored as blue. I have attached screenshots. This is the only block (including sub_block) written in VHDL. Unfortunately, that is a slow process for europractice users to register for customer support.

    Best regards,

    Rizwan 

  • in reply to riahm

    I get a similar error if I don't have the required VHDL libraries included in my cds.lib :

    Invoking the VHDL compiler to generate the parent-child information for cellview (myvhdl four_bit_adder behavioral) ...
    xmvhdl(64): 18.09-s013: (c) Copyright 1995-2019 Cadence Design Systems, Inc.

    xmvhdl_p: *F,NOLSTD: logical library name STD must be mapped to a design library [11.2].

    *WARNING* Object: myvhdl.four_bit_adder(behavioral) pc.db cannot be opened
    ERROR (HED-1073): Failed to open parent-child database for cellview (myvhdl four_bit_adder behavioral).

    I then added:

    SOFTINCLUDE $XLMHOME/tools/inca/files/cds.lib

    to my cds.lib and tried again ($XLMHOME is pointing at my XCELIUM installation). I now get:

    Invoking the VHDL compiler to generate the parent-child information for cellview (myvhdl four_bit_adder behavioral) ...
    xmvhdl(64): 18.09-s013: (c) Copyright 1995-2019 Cadence Design Systems, Inc.

    architecture Behavioral of Four_Bit_Adder is

    |

    xmvhdl_p: *E,ENNOFN (/export/home/andrewb/support/forum/myvhdl/four_bit_adder/behavioral/vhdl.vhd,5|41): Intermediate file for entity 'FOUR_BIT_ADDER' could not be loaded, entity may require re-analysis.

    component FA is

    |

    xmvhdl_p: *E,OPCOIS (/export/home/andrewb/support/forum/myvhdl/four_bit_adder/behavioral/vhdl.vhd,7|16): Optional keyword IS is only allowed in 93.

    *WARNING* Object: myvhdl.four_bit_adder(behavioral) pc.db cannot be opened
    ERROR (HED-1073): Failed to open parent-child database for cellview (myvhdl four_bit_adder behavioral).

    Strange - I didn't get that yesterday, but maybe one of my intermediate steps generated the pc.db at the time I imported the design. Not sure. I then created an hdl.var file in the working dir and opened the config again. The hdl.var contains:

    DEFINE XMVHDLOPTS -v93

    I still got the messages about the entity requiring re-analysis. This is possibly because I switching XCELIUM versions in the middle of my tests to pick something closer to you, so I imported with a different version to the one you're using. So I opened each entity view and then hit the "check-and-save" icon (a save icon with a green tick on it). Having done that I can then open the config and all is OK - the pc.db gets regenerated.

    May give you some clues? I had fewer problems yesterday after importing directly with the same version and picking v93 on the VHDL import form.

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    Hi Andrew,

    thank you very much for such detailed description. I try it.

    Best regards,

    Rizwan

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