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  3. how to add Verilog testbench for AMS simulation

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how to add Verilog testbench for AMS simulation

ntuzxy
ntuzxy over 6 years ago

Hi all,

I am an analog ic designer, so I am familiar with ADE instead of command line. ---- Background

Currently, I am doing mixed-signal design and I can run  AMS simulation for the config with both analog and digital block circuits.

The problem is that I only know how to simulate the config with the stimuli like vdc, vpulse, etc.  but don't know how to add Verilog testbench.

I created a symbol with testing code in the config but it doesn't work.

Would you please tell me how to add Verilog testbench for AMS simulation?  (It would be better if it works either in config/schematic or ADE)

Thanks!

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  • ntuzxy
    ntuzxy over 6 years ago

    To be specific, I wan to read and write data from/to text file. It seems that the system function $readmemb or $fscanf doesn't work. 

    I verified my testbench in Modlesim and it works.

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  • riahm
    riahm over 6 years ago in reply to ntuzxy

    Hi, you can make a new digital library and import all the verilog files in it including the test bench. Virtuoso>file>import>verilog. Open a schematic view, instantiate the top level analog module and the verilog test bench. create a config file. Use functional view for verilog files in the config view. After that create an ADE and run transient simulation for the time window you need.

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