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The veriloga code when simulted in cadence shows the following error though all the syntax and identifiers match the accellera. Thanks in advance.

Avieee

While running the simulation of veriloga code in cadence, I am getting the following error. And, Also the second problem was that the parameter defined using the syntax "parameter real _____"
is not being fed from the veriloga itself which I sorted out by manually entering the parameters in ADL XL.

Error found by spectre during circuit read-in.
ERROR (SFE-874): "input.scs" 10: Unexpected equals "=".

Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045.scs
Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045_mos.scs
Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045_diode.scs
Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045_bipolar.scs
Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045_mimcap.scs
Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045_moscap.scs
Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045_resistor.scs
Reading file: /cad/FOUNDRY/analog/45nm/models/spectre/gpdk045_inductor.scs
Reading file: /home/nano/DIC_project/S2d_new/veriloga/veriloga.va
Reading file: /cad/MMSIM131/tools.lnx86/spectre/etc/ahdl/constants.vams
Reading file: /cad/MMSIM131/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Time for NDB Parsing: CPU = 445.528 ms, elapsed = 499.365 ms.
Time accumulated: CPU = 479.52 ms, elapsed = 499.371 ms.
Peak resident memory used = 51.2 Mbytes.

Time for parsing: CPU = 16 us, elapsed = 15.0204 us.
Time accumulated: CPU = 479.685 ms, elapsed = 499.536 ms.
Peak resident memory used = 51.2 Mbytes.


Aggregate audit (4:50:55 PM, Sat Jun 1, 2019):
Time used: CPU = 496 ms, elapsed = 516 ms, util. = 96.1%.
Time spent in licensing: elapsed = 72.1 ms, percentage of total = 14%.
Peak memory used = 51.2 Mbytes.
Simulation started at: 4:50:54 PM, Sat Jun 1, 2019, ended at: 4:50:55 PM, Sat Jun 1, 2019, with elapsed time (wall clock): 516 ms.
spectre completes with 1 error, 0 warnings, and 0 notices.
spectre terminated prematurely due to fatal error.

Below is the input.scs file corresponding to the simulation

// Generated for: spectre
// Generated on: Jun 1 14:58:29 2019
// Design library name: DIC_project
// Design cell name: S2d_new_tb
// Design view name: schematic
simulator lang=spectre
global 0
parameters LG=.1e-6 LOV=0 typ=1 Vgs0_e=.5 Vgs0_h=.5 Vbs0_e=0 Vbs0_h=0 \
m0=9.1e-31 meff_h_K= 5.8240e-31
meff_e_Q=5.733e-31 meff_h_Q=0 g_e_K=2 g_h_K=2 q=1.60218e-19 Eg_e= \
2.8839e-19
Eg_h= 2.6917e-19
h_bar=105.457180027e-36 g_Q=6 E_KQ_h=0 Rch=200 Rce=200 eps=8.854187e-12 \
eps_t=1.1068e-10 TTOP=40e-9 eps_b= 3.4531e-11
TBOX=270e-9 FcH=100e6 FcE=20e6 W=1e-6 kox=1.4 Rcox=1.2e-8 ksi=140 L=.1e-6 \
Weff= 1.5400e-06
Rth_ox=.1360 Rth_int= 0.0120
Rth_si= 9.1008e-04
x=0 Eg=288.39z E_KQ_e= 2.0828e-20
meff_Q= 5.7330e-31
meff_K= 4.0950e-31
g_K=2 meff_e_K= 4.0950e-31

include "/cad/FOUNDRY/analog/45nm/gpdk045/../models/spectre/gpdk045.scs" section=mc

// Library name: DIC_project
// Cell name: S2d_new_tb
// View name: schematic
I0 (net4 net3 0) s2ds_120 str=1 typ=1 SELFHEAT=0 HIFIELD=0 GATEFIELD=0 \
version=1.1 W=1e-06 LG=1e-07 LOV=0 L=(LG)-((2)*(LOV)) TS=6.5e-10 \
TTOP=4e-08 TBOX=2.7e-07 tp=4e-08 Vgs0_h=0.5 Vgs0_e=0.5 \
Vgs0=((typ)==(1))?(Vgs0_e):(Vgs0_h) Vbs0_h=0 Vbs0_e=0 \
Vbs0=((typ)==(1))?(Vbs0_e):(Vbs0_h) m0=9.1e-31 \
meff_e_K=(0.45)*(m0) meff_h_K=(0.64)*(m0) \
meff_K=((typ)==(1))?(meff_e_K):(meff_h_K) meff_e_Q=(0.63)*(m0) \
meff_h_Q=0 meff_Q=((typ)==(1))?(meff_e_Q):(meff_h_Q) g_e_K=2 \
g_h_K=2 g_K=((typ)==(1))?(g_e_K):(g_h_K) g_Q=6 q=1.60219e-19 \
Eg_e=(1.8)*(q) Eg_h=(1.68)*(q) Eg=((typ)==(1))?(Eg_e):(Eg_h) \
h_bar=1.05457e-34 \
DOS_K=((meff_K)*(g_K))/(((3.14159)*(h_bar))*(h_bar)) \
DOS_Q=((g_Q)*(meff_Q))/(((3.14159)*(h_bar))*(h_bar)) \
E_KQ_e=(0.13)*(q) E_KQ_h=0 E_KQ=((typ)==(1))?(E_KQ_e):(E_KQ_h) \
Nimp=1e+14 Dtrap=1e+16 Etrap=(q)*(0.125) E0=(Eg)/(2) Vbs=40 \
Rch=200 Rce=200 \
Rc=(((0.5)*((1)-(typ)))*(Rch))+(((0.5)*((1)+(typ)))*(Rce)) \
eps=8.85419e-12 eps_t=(12.5)*(eps) eps_b=(3.9)*(eps) \
eps_TMD=((((0.5)*((1)-(typ)))*(5.16))*(eps))+((((0.5)*((1)+(typ)))*(3.3))*(eps)) \
Tnom=27 kb=1.38062e-23 CTOP=(eps_t)/(TTOP) CBOX=(eps_b)/(TBOX) \
lambda=0.1 gamma_e=2 gamma_h=1 FcE=2e+07 FcH=1e+08 \
Fc=(((0.5)*((1)-(typ)))*(FcH))+(((0.5)*((1)+(typ)))*(FcE)) \
vsat0=22000 E_pho=(0.048)*(q) \
F_per_c=(((0.5)*((1)-(typ)))*(3.02e+08))+(((0.5)*((1)+(typ)))*(9e+07)) \
Falpha=(((0.5)*((1)-(typ)))*(6.8))+(((0.5)*((1)+(typ)))*(1.45)) \
Cth=0 kox=1.4 ksi=140 Rcox=1.2e-08 Weff=(W)+((TBOX)*(2)) CTOPh=0 \
Rth_ox=(1)/((((3.14159)*(kox))/(ln((6)*(((TBOX)/(W))+(1)))))+(((kox)/(TBOX))*(W))) \
Rth_int=(Rcox)/(W) Rth_si=((1)/((2)*(ksi)))*(sqrt((L)/(Weff))) \
Rth=(((Rth_ox)+(Rth_int))+(Rth_si))/(L)
V1 (net3 0) vsource dc=x type=dc
V0 (net4 0) vsource dc=2 type=dc
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
dc dc param=x start=0 stop=10 write="spectre.dc" oppoint=rawfile \
maxiters=150 maxsteps=10000 annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save net3 I0:d
saveOptions options save=allpub
ahdl_include "/home/nano/DIC_project/S2d_new/veriloga/veriloga.va"

Parents

  • It's unclear where the problem lies because there's some line-wrapping in the input.scs which I suspect isn't there in practice. 

    Can you post the input.scs and the VerilogA as an attachment on the post (Insert->Image/video/file) so that I can try it out properly? I assume it's MMSIM13.1 you're using, but can you please provide the exact spectre subversion ("spectre -W" from UNIX will tell you, or it's at the very top of the spectre log file in ADE). Is there a good reason why you're using a 6 year old simulator version?

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    Please find the input.scs & verilogA file in the link shared below.

    input.scs

    verilogA file

    Spectre subversion-- sub-version 13.1.0.130.isr4

  • in reply to Avieee

    Something is very odd about this netlist. It doesn't look to me as if the parameters statements at the top of the input.scs were generated by ADE because there are lots of additional spaces in strange places, and there are line continuation characters missing:

    Note that I didn't point the arrow at all the missing line continuation characters (just a few). The spaces aren't a problem, but I've not seen ADE do this before.

    I fixed the missing line continuation characters (I commented out the gpdk model include since they weren't used, but that wouldn't be an issue), and here's the modified file. This simulates fine (I have no idea whether the results are correct - I didn't check - it just runs to completion):

    https://community.cadence.com/cfs-file/__key/communityserver-discussions-components-files/92/forum67.scs

    How did the parameters get generated? You mentioned ADE XL - which IC version are you using (Help->About in any window will tell you the subversion)? Perhaps you can show your variable setup in ADE XL?

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    We have defined the parameters in the verilogA file but while running it with cadence the default values are not being taken so we entered it manually.

    We got following error at first while running it without manual entry of data.

    and when we clicked ok, we got following errors though input.scs file has all the values defined

    Then we entered the datas manually in design variables section in ADE L.

    The IC version of the cadence is as follows:

    Which MMSIM shall I use, I didn't get the MMSIM's new version on the cadence downloads site?

Reply
  • in reply to Andrew Beckett

    We have defined the parameters in the verilogA file but while running it with cadence the default values are not being taken so we entered it manually.

    We got following error at first while running it without manual entry of data.

    and when we clicked ok, we got following errors though input.scs file has all the values defined

    Then we entered the datas manually in design variables section in ADE L.

    The IC version of the cadence is as follows:

    Which MMSIM shall I use, I didn't get the MMSIM's new version on the cadence downloads site?

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