I have been using ams as simulator for a mixed-signal circuit and it all worked fine. Due to the complexity of my system, I changed the views of digital std cells from schematic to Verilog in the configuration file to save some simulation time. However, when I am doing this, I am getting an error as follow:
ncelab: *F,OSDINF (./netlist.vams,650|144): instance 'ABC@XYZ<module>.I27' of design unit 'S2LINVV1D0H' is a leaf instance and is unresolved in cellview 'ABC.XYZ.schematic'.
I have also added the digital standard libraries into the library list of the config file, but nothing seems to help... and yes, I am updating the hierarchy.