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DNL/INL Using Cadence ahdlLib blocks for ADC

growingmind

Hello,

I want to use the DNL/INL AHDL blocks in ahdllib in Cadence to measure the DNL/INL of an ADC.

I use the ideal DAC to convert to digital then add the DNL or INL ahdlLIb block and a file is outputted ?

What is outputted in these files for DNL/INL ? Do I have to post-process the outputs?

If anyone has done this using the ahdlLib blocks please let me know.

I know in the latest versions of Cadence DFII (IC6.17), you can generate histogram plots using VIVA Waveform Viewer, is this helpful to generate INL/DNL ?

Can I do post processing directly in Cadence on this histogram or do I have to output the file from Cadence and then use MATLAB for post - processing ?

Is the format of the Cadence output file have to be altered for MATLAB ?

Finally, I notice there is an ADC Rapid Adoption Kit for a SAR ADC, but it omits the INL/DNL measurements.

Any chance a new RAK can be created that covers the INL/DNL measurements ?  Just wondering.



Thank you.

Parents

  • I don't believe there's a RAK on this. To be honest, I think the simplest way would be to ramp the ADC input, convert back to analog using an ideal DAC and then use the dnl or inl functions in the calculator (use right mouse->Help over each function to get a decent explanation of each).

    This is probably simpler than using the ahdlLib adc_dnl_8bit component etc (the only info is in the comments - I don't recall trying them out myself).

    Andrew.

Reply

  • I don't believe there's a RAK on this. To be honest, I think the simplest way would be to ramp the ADC input, convert back to analog using an ideal DAC and then use the dnl or inl functions in the calculator (use right mouse->Help over each function to get a decent explanation of each).

    This is probably simpler than using the ahdlLib adc_dnl_8bit component etc (the only info is in the comments - I don't recall trying them out myself).

    Andrew.

Children
  • in reply to Andrew Beckett

    HI Andrew,

    Thanks for you help.

    What are the recommandation for the slope ramp ? For example an 8 bit adc over 1.2V range and 12M sampling ? It should be 56.25e3 V/s ? 1.2/(256*1/12M) or slower ?

    A RAK is available for ENOB simulation but not for INL/DNL and many questions are found on the web without clear answer.

    Thanks in advance for your help.

    Chris

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