I am seeing bunch of cells inside Virtuoso which are named as "$unit_0x*". There is a view inside all these cells with a name "compilation_unit". It just has systemVerilog code copied from other SV views. Does anyone know why all these views are created inside dfII database? Is there a setting inside Virtuoso not to create these views? These views are getting checked in inside DM accidentally and creating a lot of mess.
I found a discussion about this in another case:
Reason: Whenever we include a systemVerilog package some extra cells get created with the prefix of $unit_. Broadly, these intermediate files are produced as a result non-design unit declarations in the "compilation unit scope" which is the region between design units (like modules). The compilation unit scope doesn't have a name (it is anonymous), so we synthesize a name for it beginning with '$unit'. These cannot be removed because other intermediate files depend on them.
We probably need to see the SystemVerilog code to see if this is truly the case - I'd suggest you contact customer support for this.
I verified that all the compilation units have "import cds_rnm_pakg::*" inside them. I have also attached one of the SV codes as an example. Cant these views not be dumped inside ".pcdb/" directory outside virtuoso environment? That seems logical step to me instead of creating view inside virtuoso library database. I have lot of SV views including "cds_rnm" package and it creates one "$unit_" view for every one of them.
I will also follow up with Cadence support on this.
Thanks for the additional info.
Rather than me look at it as well as whoever picks this up in customer support, I'll leave it to my colleague who picks this up (I don't have the bandwidth to do work that somebody else is going to do, especially as this will quite likely need a CCR to see if R&D can change the existing behaviour, and that really needs to be tied to you as a customer).