How to get AMS Simulator to ignore supply nets when using verilog models of standard cells

I am trying to run a mixed analog and digital simulation that includes standard cells with HDL views.  I can run all analog simulation fine, but I want to speed up and use the HDL view for the standard cells. I imagine this is a common methodology, but I couldn't find the answer in my searches.

Specifically, I need to know how to include standard cell digital blocks, like 'BUF_6', 'AND_2' etc, from a verilog standard cell lib into my mixed signals simulation using the AMS Simulator. I searched and saw related posts to using VerilogIn but in my case, I already have he standard cells provided by foundary in a cadence analog library with verilog switch view, and I have the foundry provided verilog models.

In schematics I have wires connecting to the logic symbol supply pins.  For example, my netlist is:

            XXXXX_BUF_6 I1 ( .VDD(VDD), .X(out1), .A(in1), .VSS(VSS), .VBN(VBN), .VBP(VBP));

In ADE under 'Simulation -> Options -> AMS Simulator'  under 'Library files (-v)'  I include the lib file XXXXX.v

The verilog lib file XXXXX.v has the following code for the standard cell

module XXXXX_BUF_6 (X, A);
output X;
input A;

`ifdef VIRL_functiononly

`else

specify
(A +=> X)=(0, 0);
endspecify
`endif

endmodule

So the verilog only defines input and output.  I am guessing there must be a way to get the AMS simulator to ignore the VDD, VSS connections from the schematic??

How do I tell the simulator to handle the supplies?

Thanks,

Makelo