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Generate verilog cellview for use in AMS from schematic of standard cell

Quantum Chip

Is it possible to generate a verilog or other cellview for use in AMS from a schematic constructed from standard cells (TSMC cells, in this case)? I want to improve mixed-mode simulation time by extracting a digital representation of this portion of the circuit. 

Apologies if this is a dumb question; I'm a bit of a novice. This seems like this should be straight-forward, if somewhat in reverse of the typical use, but I've spent hours going through documentation had trouble getting traction on this particular use-case.  If anyone can point me in the right direction, it would be appreciated. 

  • If you have a schematic containing instances of standard cells, then the Verilog-AMS netlist produced already is a Verilog netlist of the gates. The question is whether you have verilog models of the standard cells, or whether it is net listing the schematics of those standard cells and hence simulating down to transistor level.

    So, are there any verilog textual views of the standard cells in your library? If so, what are the views called? If not, what view names are available? Do you have a text file somewhere outside of Virtuoso containing Verilog descriptions of these standard cells?

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    Hi Andrew,

    Thanks for the reply. The standard cell library does not inself have verilog cellviews, but rather I have a single seperate text file that defines the verilog for all standard cells. I had thought that pointing the desired cell-views to this file in the hierarchy editor and then running the simulation based on this config file would do what I need, but it has thus far failed for me. The error it gives is: 

    xmelab: *F,CUHUNL: Instance 'I25' of cellview 'tcbn65lplvt.DFQD1LVT:module' was set to be stop view in Cadence Hierarchy Editor(HED) but this instance has hierarchy beneath it.

    The verilog code itself instantiates other modules and primitives defined in the same file. I had assumed that the hiearchy editor or netlister would be able to parse this, but maybe that is wrong? It seems like this should be simple, but I seem to be missing something.  

  • in reply to Quantum Chip

    I should mention that I have not myself specified this cell as a stop view, nor do any other lower level hierachy cells appear in the hierarchy editor after saving.

  • in reply to Quantum Chip

    Which IC version are you using? (Help->About will give the sub-version). Also, in ADE, which netlister choice have you picked for Simulation->Netlist and Run Options? Can you also show a screenshot of how you've configured some of the cells in the hierarchy editor?

    To be honest, this would probably be much more quickly resolved by going to customer support as a quick screen sharing session would allow these issues to be ironed out quickly.

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    IC6.1.8-64b.500.5. AMS Unified Netlister with xrun (the only option when using ams as simulator, it seems)

    Ok, I'll try opening a support case and see if they can figure it out. Thanks for your help.

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