Is it possible to create and simulate a SystemC cell view within the Virtuoso ADE environment. I can easily create Verilog-AMS views in Virtuoso and simulate them using the AMS simulator. This just seems to run a co-simulation between Xcelium (xrun) and Spectre. I can also compile and simulate the SystemC module in Xcelium (xrun). It would therefore seem logical that I should be able to use the AMS simulator within Virtuoso ADE to simulate mixed signal designs that include SystemC blocks. However, I don't see an option for SystemC cell views.