I'm doing whole chip function verification with verilog ams. Because the chip is big and the simulation time limitation, we decided to just use traditional verilog + wreal. For other blocks, it's no problem. But when I come to current bias, it seems I cannot check whether the current bias is connected to multiple load blocks by mistake. Unlike voltage bias, the current bias can only be connected to one load block to provide current bias. But in our previous design, we did make the mistake by connecting one current bias to 4 blocks and each block only get 1/4 of the required current. After that mistake, we did eye check to catch this mistake in later projects. And now we want to use model to check it. But after some study, I found maybe only verilog-A model can catch it. wreal won't help.
Am I right? Any suggestion. Will verilog-A model slow down the whole simulation a lot even only in bias block?